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-rw-r--r--src/intel/blorp/blorp.c4
-rw-r--r--src/intel/blorp/blorp.h13
-rw-r--r--src/intel/blorp/blorp_genX_exec.h3
-rw-r--r--src/intel/vulkan/anv_blorp.c18
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp.c12
5 files changed, 32 insertions, 18 deletions
diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c
index 91513a0413a..08afffe06d1 100644
--- a/src/intel/blorp/blorp.c
+++ b/src/intel/blorp/blorp.c
@@ -45,10 +45,12 @@ blorp_finish(struct blorp_context *blorp)
void
blorp_batch_init(struct blorp_context *blorp,
- struct blorp_batch *batch, void *driver_batch)
+ struct blorp_batch *batch, void *driver_batch,
+ enum blorp_batch_flags flags)
{
batch->blorp = blorp;
batch->driver_batch = driver_batch;
+ batch->flags = flags;
}
void
diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
index b178ae374d6..0c64d13371b 100644
--- a/src/intel/blorp/blorp.h
+++ b/src/intel/blorp/blorp.h
@@ -67,13 +67,24 @@ void blorp_init(struct blorp_context *blorp, void *driver_ctx,
struct isl_device *isl_dev);
void blorp_finish(struct blorp_context *blorp);
+enum blorp_batch_flags {
+ /**
+ * This flag indicates that blorp should *not* re-emit the depth and
+ * stencil buffer packets. Instead, the driver guarantees that all depth
+ * and stencil images passed in will match what is currently set in the
+ * hardware.
+ */
+ BLORP_BATCH_NO_EMIT_DEPTH_STENCIL = (1 << 0),
+};
+
struct blorp_batch {
struct blorp_context *blorp;
void *driver_batch;
+ enum blorp_batch_flags flags;
};
void blorp_batch_init(struct blorp_context *blorp, struct blorp_batch *batch,
- void *driver_batch);
+ void *driver_batch, enum blorp_batch_flags flags);
void blorp_batch_finish(struct blorp_batch *batch);
struct blorp_address {
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index fa5cebf8242..ec0d0223ad3 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1343,7 +1343,8 @@ blorp_exec(struct blorp_batch *batch, const struct blorp_params *params)
blorp_emit_viewport_state(batch, params);
- blorp_emit_depth_stencil_config(batch, params);
+ if (!(batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL))
+ blorp_emit_depth_stencil_config(batch, params);
blorp_emit(batch, GENX(3DPRIMITIVE), prim) {
prim.VertexAccessType = SEQUENTIAL;
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index f149f849426..d7a1fd37584 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -182,7 +182,7 @@ void anv_CmdCopyImage(
ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
struct blorp_batch batch;
- blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer);
+ blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
for (unsigned r = 0; r < regionCount; r++) {
VkOffset3D srcOffset =
@@ -244,7 +244,7 @@ copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
bool buffer_to_image)
{
struct blorp_batch batch;
- blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer);
+ blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
struct {
struct blorp_surf surf;
@@ -404,7 +404,7 @@ void anv_CmdBlitImage(
}
struct blorp_batch batch;
- blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer);
+ blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
for (unsigned r = 0; r < regionCount; r++) {
const VkImageSubresourceLayers *src_res = &pRegions[r].srcSubresource;
@@ -575,7 +575,7 @@ void anv_CmdCopyBuffer(
ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
struct blorp_batch batch;
- blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer);
+ blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
for (unsigned r = 0; r < regionCount; r++) {
uint64_t src_offset = src_buffer->offset + pRegions[r].srcOffset;
@@ -636,7 +636,7 @@ void anv_CmdUpdateBuffer(
ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
struct blorp_batch batch;
- blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer);
+ blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
/* We can't quite grab a full block because the state stream needs a
* little data at the top to build its linked list.
@@ -685,7 +685,7 @@ void anv_CmdFillBuffer(
struct isl_surf isl_surf;
struct blorp_batch batch;
- blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer);
+ blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
if (fillSize == VK_WHOLE_SIZE) {
fillSize = dst_buffer->size - dstOffset;
@@ -767,7 +767,7 @@ void anv_CmdClearColorImage(
static const bool color_write_disable[4] = { false, false, false, false };
struct blorp_batch batch;
- blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer);
+ blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
union isl_color_value clear_color;
memcpy(clear_color.u32, pColor->uint32, sizeof(pColor->uint32));
@@ -857,7 +857,7 @@ void anv_CmdResolveImage(
ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
struct blorp_batch batch;
- blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer);
+ blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
for (uint32_t r = 0; r < regionCount; r++) {
assert(pRegions[r].srcSubresource.aspectMask ==
@@ -902,7 +902,7 @@ anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer)
return;
struct blorp_batch batch;
- blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer);
+ blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
for (uint32_t i = 0; i < subpass->color_count; ++i) {
uint32_t src_att = subpass->color_attachments[i];
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 23fe3aa3f9a..94845746d25 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -388,7 +388,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
};
struct blorp_batch batch;
- blorp_batch_init(&brw->blorp, &batch, brw);
+ blorp_batch_init(&brw->blorp, &batch, brw, 0);
blorp_blit(&batch, &src_surf, src_level,
physical_to_logical_layer(src_mt, src_layer),
brw_blorp_to_isl_format(brw, src_format, false), src_isl_swizzle,
@@ -447,7 +447,7 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
&dst_level, &tmp_surfs[2]);
struct blorp_batch batch;
- blorp_batch_init(&brw->blorp, &batch, brw);
+ blorp_batch_init(&brw->blorp, &batch, brw, 0);
blorp_copy(&batch, &src_surf, src_level, src_layer,
&dst_surf, dst_level, dst_layer,
src_x, src_y, dst_x, dst_y, src_width, src_height);
@@ -852,7 +852,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
irb->mt, irb->mt_level, irb->mt_layer, num_layers);
struct blorp_batch batch;
- blorp_batch_init(&brw->blorp, &batch, brw);
+ blorp_batch_init(&brw->blorp, &batch, brw, 0);
blorp_fast_clear(&batch, &surf,
(enum isl_format)brw->render_target_format[format],
level, irb_logical_mt_layer(irb), num_layers,
@@ -872,7 +872,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
memcpy(clear_color.f32, ctx->Color.ClearColor.f, sizeof(float) * 4);
struct blorp_batch batch;
- blorp_batch_init(&brw->blorp, &batch, brw);
+ blorp_batch_init(&brw->blorp, &batch, brw, 0);
blorp_clear(&batch, &surf,
(enum isl_format)brw->render_target_format[format],
ISL_SWIZZLE_IDENTITY,
@@ -944,7 +944,7 @@ brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt)
blorp_surf_for_miptree(brw, &surf, mt, true, &level, isl_tmp);
struct blorp_batch batch;
- blorp_batch_init(&brw->blorp, &batch, brw);
+ blorp_batch_init(&brw->blorp, &batch, brw, 0);
blorp_ccs_resolve(&batch, &surf,
brw_blorp_to_isl_format(brw, format, true));
blorp_batch_finish(&batch);
@@ -966,7 +966,7 @@ gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
blorp_surf_for_miptree(brw, &surf, mt, true, &level, isl_tmp);
struct blorp_batch batch;
- blorp_batch_init(&brw->blorp, &batch, brw);
+ blorp_batch_init(&brw->blorp, &batch, brw, 0);
blorp_gen6_hiz_op(&batch, &surf, level, layer, op);
blorp_batch_finish(&batch);
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 12:23:59 +0000