diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/vc4/vc4_blit.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/gallium/drivers/vc4/vc4_blit.c b/src/gallium/drivers/vc4/vc4_blit.c index 876c296dc85..128a3e50ee2 100644 --- a/src/gallium/drivers/vc4/vc4_blit.c +++ b/src/gallium/drivers/vc4/vc4_blit.c @@ -88,6 +88,26 @@ vc4_tile_blit(struct pipe_context *pctx, const struct pipe_blit_info *info) return false; } + /* VC4_PACKET_LOAD_TILE_BUFFER_GENERAL uses the + * VC4_PACKET_TILE_RENDERING_MODE_CONFIG's width (determined by our + * destination surface) to determine the stride. This may be wrong + * when reading from texture miplevels > 0, which are stored in + * POT-sized areas. For MSAA, the tile addresses are computed + * explicitly by the RCL. + */ + if (info->src.resource->nr_samples <= 1) { + struct vc4_resource *rsc = vc4_resource(info->src.resource); + + uint32_t stride = dst_surface_width * rsc->cpp; + if (rsc->slices[info->src.level].tiling == VC4_TILING_FORMAT_T) + stride = align(stride, 128); + else + stride = align(stride, 16); + + if (stride != rsc->slices[info->src.level].stride) + return false; + } + if (info->dst.resource->format != info->src.resource->format) return false; |