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-rw-r--r--src/intel/compiler/brw_vec4_generator.cpp8
-rw-r--r--src/intel/compiler/brw_vec4_nir.cpp1
2 files changed, 1 insertions, 8 deletions
diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp
index e1a12ba5ffe..65f3a9a9f00 100644
--- a/src/intel/compiler/brw_vec4_generator.cpp
+++ b/src/intel/compiler/brw_vec4_generator.cpp
@@ -1961,14 +1961,6 @@ generate_code(struct brw_codegen *p,
src[0].width = BRW_WIDTH_4;
brw_MOV(p, spread_dst, src[0]);
- /* As we have set horizontal stride 1 instead of 2 in IVB/BYT, we
- * need to fix it here to have the expected value.
- */
- if (devinfo->gen == 7 && !devinfo->is_haswell)
- spread_dst = stride(dst, 8, 4, 2);
-
- brw_MOV(p, dst, spread_dst);
-
brw_set_default_access_mode(p, BRW_ALIGN_16);
break;
}
diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp
index 6dd5789225d..64371a16de5 100644
--- a/src/intel/compiler/brw_vec4_nir.cpp
+++ b/src/intel/compiler/brw_vec4_nir.cpp
@@ -1191,6 +1191,7 @@ vec4_visitor::emit_conversion_from_double(dst_reg dst, src_reg src,
emit(VEC4_OPCODE_FROM_DOUBLE, temp2, src_reg(temp))
->size_written = 2 * REG_SIZE;
+ emit(VEC4_OPCODE_PICK_LOW_32BIT, temp2, src_reg(retype(temp2, BRW_REGISTER_TYPE_DF)));
vec4_instruction *inst = emit(MOV(dst, src_reg(temp2)));
inst->saturate = saturate;
}