diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_context.c | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_screen.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_screen.h | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_state.c | 46 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/server/radeon_reg.h | 6 |
5 files changed, 56 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index 9231697a49e..5f0e2d18d55 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -132,6 +132,7 @@ static const char * const card_extensions[] = "GL_EXT_blend_logic_op", "GL_EXT_blend_subtract", "GL_EXT_secondary_color", + "GL_EXT_stencil_wrap", "GL_EXT_texture_edge_clamp", "GL_EXT_texture_env_combine", "GL_EXT_texture_env_dot3", diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 3d3538ab3d5..8346209c9a1 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -312,6 +312,8 @@ radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv ) case PCI_CHIP_RADEON_QE: case PCI_CHIP_RADEON_QF: case PCI_CHIP_RADEON_QG: + /* all original radeons (7200) presumably have a stencil op bug */ + screen->chipset |= RADEON_CHIPSET_BROKEN_STENCIL; case PCI_CHIP_RV200_QW: case PCI_CHIP_RV200_QX: case PCI_CHIP_RADEON_LW: diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h b/src/mesa/drivers/dri/radeon/radeon_screen.h index 1351bb29799..edd4a08f818 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.h +++ b/src/mesa/drivers/dri/radeon/radeon_screen.h @@ -58,6 +58,7 @@ typedef struct { /* chipset features */ #define RADEON_CHIPSET_TCL (1 << 0) +#define RADEON_CHIPSET_BROKEN_STENCIL (1 << 1) typedef struct { diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 851b62035a5..3d0eda3a07e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -1332,6 +1332,34 @@ static void radeonStencilOp( GLcontext *ctx, GLenum fail, { radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + /* radeon 7200 have stencil bug, DEC and INC_WRAP will actually both do DEC_WRAP, + and DEC_WRAP (and INVERT) will do INVERT. No way to get correct INC_WRAP and DEC, + but DEC_WRAP can be fixed by using DEC and INC_WRAP at least use INC. */ + + GLuint tempRADEON_STENCIL_FAIL_DEC_WRAP; + GLuint tempRADEON_STENCIL_FAIL_INC_WRAP; + GLuint tempRADEON_STENCIL_ZFAIL_DEC_WRAP; + GLuint tempRADEON_STENCIL_ZFAIL_INC_WRAP; + GLuint tempRADEON_STENCIL_ZPASS_DEC_WRAP; + GLuint tempRADEON_STENCIL_ZPASS_INC_WRAP; + + if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_BROKEN_STENCIL) { + tempRADEON_STENCIL_FAIL_DEC_WRAP = RADEON_STENCIL_FAIL_DEC; + tempRADEON_STENCIL_FAIL_INC_WRAP = RADEON_STENCIL_FAIL_INC; + tempRADEON_STENCIL_ZFAIL_DEC_WRAP = RADEON_STENCIL_ZFAIL_DEC; + tempRADEON_STENCIL_ZFAIL_INC_WRAP = RADEON_STENCIL_ZFAIL_INC; + tempRADEON_STENCIL_ZPASS_DEC_WRAP = RADEON_STENCIL_ZPASS_DEC; + tempRADEON_STENCIL_ZPASS_INC_WRAP = RADEON_STENCIL_ZPASS_INC; + } + else { + tempRADEON_STENCIL_FAIL_DEC_WRAP = RADEON_STENCIL_FAIL_DEC_WRAP; + tempRADEON_STENCIL_FAIL_INC_WRAP = RADEON_STENCIL_FAIL_INC_WRAP; + tempRADEON_STENCIL_ZFAIL_DEC_WRAP = RADEON_STENCIL_ZFAIL_DEC_WRAP; + tempRADEON_STENCIL_ZFAIL_INC_WRAP = RADEON_STENCIL_ZFAIL_INC_WRAP; + tempRADEON_STENCIL_ZPASS_DEC_WRAP = RADEON_STENCIL_ZPASS_DEC_WRAP; + tempRADEON_STENCIL_ZPASS_INC_WRAP = RADEON_STENCIL_ZPASS_INC_WRAP; + } + RADEON_STATECHANGE( rmesa, ctx ); rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~(RADEON_STENCIL_FAIL_MASK | RADEON_STENCIL_ZFAIL_MASK | @@ -1353,6 +1381,12 @@ static void radeonStencilOp( GLcontext *ctx, GLenum fail, case GL_DECR: rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_FAIL_DEC; break; + case GL_INCR_WRAP: + rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_FAIL_INC_WRAP; + break; + case GL_DECR_WRAP: + rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_FAIL_DEC_WRAP; + break; case GL_INVERT: rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_FAIL_INVERT; break; @@ -1374,6 +1408,12 @@ static void radeonStencilOp( GLcontext *ctx, GLenum fail, case GL_DECR: rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZFAIL_DEC; break; + case GL_INCR_WRAP: + rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_ZFAIL_INC_WRAP; + break; + case GL_DECR_WRAP: + rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_ZFAIL_DEC_WRAP; + break; case GL_INVERT: rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZFAIL_INVERT; break; @@ -1395,6 +1435,12 @@ static void radeonStencilOp( GLcontext *ctx, GLenum fail, case GL_DECR: rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZPASS_DEC; break; + case GL_INCR_WRAP: + rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_ZPASS_INC_WRAP; + break; + case GL_DECR_WRAP: + rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_ZPASS_DEC_WRAP; + break; case GL_INVERT: rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZPASS_INVERT; break; diff --git a/src/mesa/drivers/dri/radeon/server/radeon_reg.h b/src/mesa/drivers/dri/radeon/server/radeon_reg.h index 4bd4d14e783..4898dbf968b 100644 --- a/src/mesa/drivers/dri/radeon/server/radeon_reg.h +++ b/src/mesa/drivers/dri/radeon/server/radeon_reg.h @@ -1615,6 +1615,8 @@ # define RADEON_STENCIL_FAIL_INC (3 << 16) # define RADEON_STENCIL_FAIL_DEC (4 << 16) # define RADEON_STENCIL_FAIL_INVERT (5 << 16) +# define RADEON_STENCIL_FAIL_INC_WRAP (6 << 16) +# define RADEON_STENCIL_FAIL_DEC_WRAP (7 << 16) # define RADEON_STENCIL_FAIL_MASK (0x7 << 16) # define RADEON_STENCIL_ZPASS_KEEP (0 << 20) # define RADEON_STENCIL_ZPASS_ZERO (1 << 20) @@ -1622,6 +1624,8 @@ # define RADEON_STENCIL_ZPASS_INC (3 << 20) # define RADEON_STENCIL_ZPASS_DEC (4 << 20) # define RADEON_STENCIL_ZPASS_INVERT (5 << 20) +# define RADEON_STENCIL_ZPASS_INC_WRAP (6 << 20) +# define RADEON_STENCIL_ZPASS_DEC_WRAP (7 << 20) # define RADEON_STENCIL_ZPASS_MASK (0x7 << 20) # define RADEON_STENCIL_ZFAIL_KEEP (0 << 24) # define RADEON_STENCIL_ZFAIL_ZERO (1 << 24) @@ -1629,6 +1633,8 @@ # define RADEON_STENCIL_ZFAIL_INC (3 << 24) # define RADEON_STENCIL_ZFAIL_DEC (4 << 24) # define RADEON_STENCIL_ZFAIL_INVERT (5 << 24) +# define RADEON_STENCIL_ZFAIL_INC_WRAP (6 << 24) +# define RADEON_STENCIL_ZFAIL_DEC_WRAP (7 << 24) # define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24) # define RADEON_Z_COMPRESSION_ENABLE (1 << 28) # define RADEON_FORCE_Z_DIRTY (1 << 29) |