diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen6_blorp.c | 76 |
1 files changed, 2 insertions, 74 deletions
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c b/src/mesa/drivers/dri/i965/gen6_blorp.c index 1af898dba56..70dc9f6d2ad 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.c +++ b/src/mesa/drivers/dri/i965/gen6_blorp.c @@ -350,78 +350,6 @@ gen6_blorp_emit_cc_state_pointers(struct brw_context *brw, ADVANCE_BATCH(); } -/* SURFACE_STATE for renderbuffer or texture surface (see - * brw_update_renderbuffer_surface and brw_update_texture_surface) - */ -static uint32_t -gen6_blorp_emit_surface_state(struct brw_context *brw, - const struct brw_blorp_params *params, - const struct brw_blorp_surface_info *surface, - uint32_t read_domains, uint32_t write_domain) -{ - uint32_t wm_surf_offset; - uint32_t width = surface->width; - uint32_t height = surface->height; - if (surface->num_samples > 1) { - /* Since gen6 uses INTEL_MSAA_LAYOUT_IMS, width and height are measured - * in samples. But SURFACE_STATE wants them in pixels, so we need to - * divide them each by 2. - */ - width /= 2; - height /= 2; - } - struct intel_mipmap_tree *mt = surface->mt; - uint32_t tile_x, tile_y; - - uint32_t *surf = (uint32_t *) - brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, - &wm_surf_offset); - - surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT | - BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT | - BRW_SURFACE_CUBEFACE_ENABLES | - surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT); - - /* reloc */ - surf[1] = (brw_blorp_compute_tile_offsets(surface, &tile_x, &tile_y) + - mt->bo->offset64); - - surf[2] = (0 << BRW_SURFACE_LOD_SHIFT | - (width - 1) << BRW_SURFACE_WIDTH_SHIFT | - (height - 1) << BRW_SURFACE_HEIGHT_SHIFT); - - uint32_t tiling = surface->map_stencil_as_y_tiled - ? BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y - : brw_get_surface_tiling_bits(mt->tiling); - uint32_t pitch_bytes = mt->pitch; - if (surface->map_stencil_as_y_tiled) - pitch_bytes *= 2; - surf[3] = (tiling | - 0 << BRW_SURFACE_DEPTH_SHIFT | - (pitch_bytes - 1) << BRW_SURFACE_PITCH_SHIFT); - - surf[4] = brw_get_surface_num_multisamples(surface->num_samples); - - /* Note that the low bits of these fields are missing, so - * there's the possibility of getting in trouble. - */ - assert(tile_x % 4 == 0); - assert(tile_y % 2 == 0); - surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT | - (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT | - (surface->mt->valign == 4 ? - BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0)); - - /* Emit relocation to surface contents */ - drm_intel_bo_emit_reloc(brw->batch.bo, - wm_surf_offset + 4, - mt->bo, - surf[1] - mt->bo->offset64, - read_domains, write_domain); - - return wm_surf_offset; -} - /* BINDING_TABLE. See brw_wm_binding_table(). */ uint32_t @@ -1035,8 +963,8 @@ gen6_blorp_exec(struct brw_context *brw, I915_GEM_DOMAIN_RENDER, true); if (params->src.mt) { wm_surf_offset_texture = - gen6_blorp_emit_surface_state(brw, params, ¶ms->src, - I915_GEM_DOMAIN_SAMPLER, 0); + brw_blorp_emit_surface_state(brw, ¶ms->src, + I915_GEM_DOMAIN_SAMPLER, 0, false); } wm_bind_bo_offset = gen6_blorp_emit_binding_table(brw, |