diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/r600/r600_texstate.c | 6 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_common_context.c | 10 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_common_context.h | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 9 |
4 files changed, 21 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 70dd5404811..082bfd75f69 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -556,7 +556,7 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex radeonTexObj *t = radeon_tex_obj(texObj); const struct gl_texture_image *firstImage; int firstlevel = t->mt ? t->mt->firstLevel : 0; - GLuint uTexelPitch; + GLuint uTexelPitch, row_align;; firstImage = t->base.Image[0][firstlevel]; @@ -595,7 +595,9 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex return; } - uTexelPitch = (firstImage->Width + R700_TEXEL_PITCH_ALIGNMENT_MASK) + row_align = rmesa->radeon.texture_row_align - 1; + uTexelPitch = ((firstImage->Width * t->mt->bpp + row_align) & ~row_align) / t->mt->bpp; + uTexelPitch = (uTexelPitch + R700_TEXEL_PITCH_ALIGNMENT_MASK) & ~R700_TEXEL_PITCH_ALIGNMENT_MASK; /* min pitch is 8 */ diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index a50cd056e1c..4e4eba5d94c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -241,7 +241,15 @@ GLboolean radeonInitContext(radeonContextPtr radeon, radeon->texture_depth = ( glVisual->rgbBits > 16 ) ? DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; - radeon->texture_row_align = 32; + if (IS_R600_CLASS(radeon->radeonScreen)) { + radeon->texture_row_align = 256; + radeon->texture_rect_row_align = 256; + radeon->texture_compressed_row_align = 256; + } else { + radeon->texture_row_align = 32; + radeon->texture_rect_row_align = 64; + radeon->texture_compressed_row_align = 64; + } return GL_TRUE; } diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index 0cdacb1c361..cd1986e1fc3 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -429,6 +429,8 @@ struct radeon_context { int texture_depth; float initialMaxAnisotropy; uint32_t texture_row_align; + uint32_t texture_rect_row_align; + uint32_t texture_compressed_row_align; struct radeon_dma dma; struct radeon_hw_state hw; diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index f04a07fecd2..071a18e7d86 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -90,16 +90,18 @@ static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree GLuint face, GLuint level, GLuint* curOffset) { radeon_mipmap_level *lvl = &mt->levels[level]; - uint32_t row_align = rmesa->texture_row_align - 1; + uint32_t row_align; /* Find image size in bytes */ if (mt->compressed) { /* TODO: Is this correct? Need test cases for compressed textures! */ - lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63; + row_align = rmesa->texture_compressed_row_align - 1; + lvl->rowstride = (lvl->width * mt->bpp + row_align) & ~row_align; lvl->size = radeon_compressed_texture_size(mt->radeon->glCtx, lvl->width, lvl->height, lvl->depth, mt->compressed); } else if (mt->target == GL_TEXTURE_RECTANGLE_NV) { - lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63; + row_align = rmesa->texture_rect_row_align - 1; + lvl->rowstride = (lvl->width * mt->bpp + row_align) & ~row_align; lvl->size = lvl->rowstride * lvl->height; } else if (mt->tilebits & RADEON_TXO_MICRO_TILE) { /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned, @@ -108,6 +110,7 @@ static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31; lvl->size = lvl->rowstride * ((lvl->height + 1) / 2) * lvl->depth; } else { + row_align = rmesa->texture_row_align - 1; lvl->rowstride = (lvl->width * mt->bpp + row_align) & ~row_align; lvl->size = lvl->rowstride * lvl->height * lvl->depth; } |