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-rw-r--r--src/amd/vulkan/radv_device.c10
-rw-r--r--src/amd/vulkan/radv_image.c10
-rw-r--r--src/amd/vulkan/radv_meta_clear.c2
-rw-r--r--src/amd/vulkan/radv_meta_copy.c2
-rw-r--r--src/amd/vulkan/radv_private.h9
5 files changed, 21 insertions, 12 deletions
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 39e320e3771..de184603eb0 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3622,7 +3622,7 @@ radv_calc_decompress_on_z_planes(struct radv_device *device,
{
unsigned max_zplanes = 0;
- assert(iview->image->tc_compatible_htile);
+ assert(radv_image_is_tc_compat_htile(iview->image));
if (device->physical_device->rad_info.chip_class >= GFX9) {
/* Default value for 32-bit depth surfaces. */
@@ -3724,7 +3724,7 @@ radv_initialise_ds_surface(struct radv_device *device,
if (radv_htile_enabled(iview->image, level)) {
ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
- if (iview->image->tc_compatible_htile) {
+ if (radv_image_is_tc_compat_htile(iview->image)) {
unsigned max_zplanes =
radv_calc_decompress_on_z_planes(device, iview);
@@ -3752,7 +3752,7 @@ radv_initialise_ds_surface(struct radv_device *device,
z_offs += iview->image->surface.u.legacy.level[level].offset;
s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
- ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!iview->image->tc_compatible_htile);
+ ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
ds->db_stencil_info = S_028044_FORMAT(stencil_format);
@@ -3797,7 +3797,7 @@ radv_initialise_ds_surface(struct radv_device *device,
ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
if (!iview->image->surface.has_stencil &&
- !iview->image->tc_compatible_htile)
+ !radv_image_is_tc_compat_htile(iview->image))
/* Use all of the htile_buffer for depth if there's no stencil. */
ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
@@ -3806,7 +3806,7 @@ radv_initialise_ds_surface(struct radv_device *device,
ds->db_htile_data_base = va >> 8;
ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
- if (iview->image->tc_compatible_htile) {
+ if (radv_image_is_tc_compat_htile(iview->image)) {
unsigned max_zplanes =
radv_calc_decompress_on_z_planes(device, iview);
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 86d97ff83bf..b35df1d172a 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -336,8 +336,8 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
meta_va = gpu_address + image->dcc_offset;
if (chip_class <= VI)
meta_va += base_level_info->dcc_offset;
- } else if(!is_storage_image && image->tc_compatible_htile &&
- radv_image_has_htile(image)) {
+ } else if (!is_storage_image &&
+ radv_image_is_tc_compat_htile(image)) {
meta_va = gpu_address + image->htile_offset;
}
@@ -488,7 +488,7 @@ si_make_texture_descriptor(struct radv_device *device,
/* S8 with either Z16 or Z32 HTILE need a special format. */
if (device->physical_device->rad_info.chip_class >= GFX9 &&
vk_format == VK_FORMAT_S8_UINT &&
- image->tc_compatible_htile) {
+ radv_image_is_tc_compat_htile(image)) {
if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
@@ -1201,7 +1201,7 @@ bool radv_layout_has_htile(const struct radv_image *image,
VkImageLayout layout,
unsigned queue_mask)
{
- if (radv_image_has_htile(image) && image->tc_compatible_htile)
+ if (radv_image_is_tc_compat_htile(image))
return layout != VK_IMAGE_LAYOUT_GENERAL;
return radv_image_has_htile(image) &&
@@ -1214,7 +1214,7 @@ bool radv_layout_is_htile_compressed(const struct radv_image *image,
VkImageLayout layout,
unsigned queue_mask)
{
- if (radv_image_has_htile(image) && image->tc_compatible_htile)
+ if (radv_image_is_tc_compat_htile(image))
return layout != VK_IMAGE_LAYOUT_GENERAL;
return radv_image_has_htile(image) &&
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index f78b956fa12..016c1ee296e 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -553,7 +553,7 @@ static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
clear_rect->rect.extent.width != iview->extent.width ||
clear_rect->rect.extent.height != iview->extent.height)
return false;
- if (iview->image->tc_compatible_htile &&
+ if (radv_image_is_tc_compat_htile(iview->image) &&
(((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && clear_value.depth != 0.0 &&
clear_value.depth != 1.0) ||
((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && clear_value.stencil != 0)))
diff --git a/src/amd/vulkan/radv_meta_copy.c b/src/amd/vulkan/radv_meta_copy.c
index c8140b24dae..2055289a9bb 100644
--- a/src/amd/vulkan/radv_meta_copy.c
+++ b/src/amd/vulkan/radv_meta_copy.c
@@ -90,7 +90,7 @@ blit_surf_for_image_level_layer(struct radv_image *image,
format = vk_format_stencil_only(format);
if (!radv_image_has_dcc(image) &&
- !(radv_image_has_htile(image) && image->tc_compatible_htile))
+ !(radv_image_is_tc_compat_htile(image)))
format = vk_format_for_size(vk_format_get_blocksize(format));
return (struct radv_meta_blit2d_surf) {
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 97f4cf657d8..31748910ad8 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1439,6 +1439,15 @@ radv_htile_enabled(const struct radv_image *image, unsigned level)
return radv_image_has_htile(image) && level == 0;
}
+/**
+ * Return whether the image is TC-compatible HTILE.
+ */
+static inline bool
+radv_image_is_tc_compat_htile(const struct radv_image *image)
+{
+ return radv_image_has_htile(image) && image->tc_compatible_htile;
+}
+
unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
static inline uint32_t
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-14 09:38:30 +0000