4 files changed, 40 insertions, 10 deletions

diff --git a/src/intel/vulkan/anv_cmd_buffer.c b/src/intel/vulkan/anv_cmd_buffer.c
index 380260a330f..6c082aa77ef 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -738,20 +738,26 @@ anv_cmd_buffer_emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
 {
    struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
    struct anv_subpass *subpass = cmd_buffer->state.subpass;
-   struct anv_pipeline_bind_map *map;
+   struct anv_pipeline *pipeline;
    uint32_t bias, state_offset;
 
    switch (stage) {
    case  MESA_SHADER_COMPUTE:
-      map = &cmd_buffer->state.compute_pipeline->bindings[stage];
+      pipeline = cmd_buffer->state.compute_pipeline;
       bias = 1;
       break;
    default:
-      map = &cmd_buffer->state.pipeline->bindings[stage];
+      pipeline = cmd_buffer->state.pipeline;
       bias = 0;
       break;
    }
 
+   if (!anv_pipeline_has_stage(pipeline, stage)) {
+      *bt_state = (struct anv_state) { 0, };
+      return VK_SUCCESS;
+   }
+
+   struct anv_pipeline_bind_map *map = &pipeline->bindings[stage];
    if (bias + map->surface_count == 0) {
       *bt_state = (struct anv_state) { 0, };
       return VK_SUCCESS;
@@ -904,13 +910,19 @@ VkResult
 anv_cmd_buffer_emit_samplers(struct anv_cmd_buffer *cmd_buffer,
                              gl_shader_stage stage, struct anv_state *state)
 {
-   struct anv_pipeline_bind_map *map;
+   struct anv_pipeline *pipeline;
 
    if (stage == MESA_SHADER_COMPUTE)
-      map = &cmd_buffer->state.compute_pipeline->bindings[stage];
+      pipeline = cmd_buffer->state.compute_pipeline;
    else
-      map = &cmd_buffer->state.pipeline->bindings[stage];
+      pipeline = cmd_buffer->state.pipeline;
+
+   if (!anv_pipeline_has_stage(pipeline, stage)) {
+      *state = (struct anv_state) { 0, };
+      return VK_SUCCESS;
+   }
 
+   struct anv_pipeline_bind_map *map = &pipeline->bindings[stage];
    if (map->sampler_count == 0) {
       *state = (struct anv_state) { 0, };
       return VK_SUCCESS;
@@ -1077,6 +1089,10 @@ struct anv_state
 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
                               gl_shader_stage stage)
 {
+   /* If we don't have this stage, bail. */
+   if (!anv_pipeline_has_stage(cmd_buffer->state.pipeline, stage))
+      return (struct anv_state) { .offset = 0 };
+
    struct anv_push_constants *data =
       cmd_buffer->state.push_constants[stage];
    const struct brw_stage_prog_data *prog_data =
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 5fcbb92d348..6a8c6fc2bed 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1520,6 +1520,13 @@ struct anv_pipeline {
    } gen9;
 };
 
+static inline bool
+anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
+                       gl_shader_stage stage)
+{
+   return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
+}
+
 static inline const struct brw_vs_prog_data *
 get_vs_prog_data(struct anv_pipeline *pipeline)
 {
diff --git a/src/intel/vulkan/genX_l3.c b/src/intel/vulkan/genX_l3.c
index 0d36e3cd4c0..8b3b8acb098 100644
--- a/src/intel/vulkan/genX_l3.c
+++ b/src/intel/vulkan/genX_l3.c
@@ -315,10 +315,13 @@ get_pipeline_state_l3_weights(const struct anv_pipeline *pipeline)
    bool needs_dc = false, needs_slm = false;
 
    for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
+      if (!anv_pipeline_has_stage(pipeline, i))
+         continue;
+
       const struct brw_stage_prog_data *prog_data = pipeline->prog_data[i];
 
       needs_dc |= pipeline->needs_data_cache;
-      needs_slm |= prog_data && prog_data->total_shared;
+      needs_slm |= prog_data->total_shared;
    }
 
    return get_default_l3_weights(&pipeline->device->info,
diff --git a/src/intel/vulkan/genX_pipeline_util.h b/src/intel/vulkan/genX_pipeline_util.h
index c1ff6dff179..62fd01cd4b7 100644
--- a/src/intel/vulkan/genX_pipeline_util.h
+++ b/src/intel/vulkan/genX_pipeline_util.h
@@ -668,11 +668,15 @@ emit_cb_state(struct anv_pipeline *pipeline,
       blend_state.Entry[i].WriteDisableBlue = true;
    }
 
-   struct anv_pipeline_bind_map *map =
-      &pipeline->bindings[MESA_SHADER_FRAGMENT];
+   uint32_t surface_count = 0;
+   struct anv_pipeline_bind_map *map;
+   if (anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
+      map = &pipeline->bindings[MESA_SHADER_FRAGMENT];
+      surface_count = map->surface_count;
+   }
 
    bool has_writeable_rt = false;
-   for (unsigned i = 0; i < map->surface_count; i++) {
+   for (unsigned i = 0; i < surface_count; i++) {
       struct anv_pipeline_binding *binding = &map->surface_to_descriptor[i];
 
       /* All color attachments are at the beginning of the binding table */