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-rw-r--r--src/gallium/drivers/radeon/AMDIL.h75
-rw-r--r--src/gallium/drivers/radeon/AMDILCFGStructurizer.cpp24
-rw-r--r--src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp10
-rw-r--r--src/gallium/drivers/radeon/AMDILPeepholeOptimizer.cpp8
4 files changed, 26 insertions, 91 deletions
diff --git a/src/gallium/drivers/radeon/AMDIL.h b/src/gallium/drivers/radeon/AMDIL.h
index 4bd47b2797f..e96b123bb7d 100644
--- a/src/gallium/drivers/radeon/AMDIL.h
+++ b/src/gallium/drivers/radeon/AMDIL.h
@@ -8,7 +8,7 @@
//==-----------------------------------------------------------------------===//
//
// This file contains the entry points for global functions defined in the LLVM
-// AMDIL back-end.
+// AMDGPU back-end.
//
//===----------------------------------------------------------------------===//
@@ -18,9 +18,6 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetMachine.h"
-#define AMDIL_MAJOR_VERSION 2
-#define AMDIL_MINOR_VERSION 0
-#define AMDIL_REVISION_NUMBER 74
#define ARENA_SEGMENT_RESERVED_UAVS 12
#define DEFAULT_ARENA_UAV_ID 8
#define DEFAULT_RAW_UAV_ID 7
@@ -39,26 +36,6 @@
#define DEFAULT_SCRATCH_ID 1
#define DEFAULT_VEC_SLOTS 8
-// SC->CAL version matchings.
-#define CAL_VERSION_SC_150 1700
-#define CAL_VERSION_SC_149 1700
-#define CAL_VERSION_SC_148 1525
-#define CAL_VERSION_SC_147 1525
-#define CAL_VERSION_SC_146 1525
-#define CAL_VERSION_SC_145 1451
-#define CAL_VERSION_SC_144 1451
-#define CAL_VERSION_SC_143 1441
-#define CAL_VERSION_SC_142 1441
-#define CAL_VERSION_SC_141 1420
-#define CAL_VERSION_SC_140 1400
-#define CAL_VERSION_SC_139 1387
-#define CAL_VERSION_SC_138 1387
-#define CAL_APPEND_BUFFER_SUPPORT 1340
-#define CAL_VERSION_SC_137 1331
-#define CAL_VERSION_SC_136 982
-#define CAL_VERSION_SC_135 950
-#define CAL_VERSION_GLOBAL_RETURN_BUFFER 990
-
#define OCL_DEVICE_RV710 0x0001
#define OCL_DEVICE_RV730 0x0002
#define OCL_DEVICE_RV770 0x0004
@@ -76,10 +53,6 @@
/// internal compiler usage.
const unsigned int RESERVED_FUNCS = 1024;
-#define AMDIL_OPT_LEVEL_DECL
-#define AMDIL_OPT_LEVEL_VAR
-#define AMDIL_OPT_LEVEL_VAR_NO_COMMA
-
namespace llvm {
class AMDGPUInstrPrinter;
class FunctionPass;
@@ -90,17 +63,16 @@ class TargetMachine;
/// Instruction selection passes.
FunctionPass*
- createAMDGPUISelDag(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
+ createAMDGPUISelDag(TargetMachine &TM);
FunctionPass*
- createAMDGPUPeepholeOpt(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
+ createAMDGPUPeepholeOpt(TargetMachine &TM);
/// Pre emit passes.
FunctionPass*
- createAMDGPUCFGPreparationPass(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
+ createAMDGPUCFGPreparationPass(TargetMachine &TM);
FunctionPass*
- createAMDGPUCFGStructurizerPass(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
+ createAMDGPUCFGStructurizerPass(TargetMachine &TM);
-extern Target TheAMDILTarget;
extern Target TheAMDGPUTarget;
} // end namespace llvm;
@@ -128,43 +100,6 @@ enum AddressSpaces {
LAST_ADDRESS = 9
};
-// This union/struct combination is an easy way to read out the
-// exact bits that are needed.
-typedef union ResourceRec {
- struct {
-#ifdef __BIG_ENDIAN__
- unsigned short isImage : 1; // Reserved for future use/llvm.
- unsigned short ResourceID : 10; // Flag to specify the resourece ID for
- // the op.
- unsigned short HardwareInst : 1; // Flag to specify that this instruction
- // is a hardware instruction.
- unsigned short ConflictPtr : 1; // Flag to specify that the pointer has a
- // conflict.
- unsigned short ByteStore : 1; // Flag to specify if the op is a byte
- // store op.
- unsigned short PointerPath : 1; // Flag to specify if the op is on the
- // pointer path.
- unsigned short CacheableRead : 1; // Flag to specify if the read is
- // cacheable.
-#else
- unsigned short CacheableRead : 1; // Flag to specify if the read is
- // cacheable.
- unsigned short PointerPath : 1; // Flag to specify if the op is on the
- // pointer path.
- unsigned short ByteStore : 1; // Flag to specify if the op is byte
- // store op.
- unsigned short ConflictPtr : 1; // Flag to specify that the pointer has
- // a conflict.
- unsigned short HardwareInst : 1; // Flag to specify that this instruction
- // is a hardware instruction.
- unsigned short ResourceID : 10; // Flag to specify the resource ID for
- // the op.
- unsigned short isImage : 1; // Reserved for future use.
-#endif
- } bits;
- unsigned short u16all;
-} InstrResEnc;
-
} // namespace AMDGPUAS
} // end namespace llvm
diff --git a/src/gallium/drivers/radeon/AMDILCFGStructurizer.cpp b/src/gallium/drivers/radeon/AMDILCFGStructurizer.cpp
index 40e62273bda..95a75ac0ffc 100644
--- a/src/gallium/drivers/radeon/AMDILCFGStructurizer.cpp
+++ b/src/gallium/drivers/radeon/AMDILCFGStructurizer.cpp
@@ -2636,7 +2636,7 @@ protected:
const AMDGPURegisterInfo *TRI;
public:
- AMDGPUCFGStructurizer(char &pid, TargetMachine &tm AMDIL_OPT_LEVEL_DECL);
+ AMDGPUCFGStructurizer(char &pid, TargetMachine &tm);
const TargetInstrInfo *getTargetInstrInfo() const;
//bool runOnMachineFunction(MachineFunction &F);
@@ -2647,7 +2647,7 @@ private:
//char AMDGPUCFGStructurizer::ID = 0;
} //end of namespace llvm
AMDGPUCFGStructurizer::AMDGPUCFGStructurizer(char &pid, TargetMachine &tm
- AMDIL_OPT_LEVEL_DECL)
+ )
: MachineFunctionPass(pid), TM(tm), TII(tm.getInstrInfo()),
TRI(static_cast<const AMDGPURegisterInfo *>(tm.getRegisterInfo())
) {
@@ -2673,7 +2673,7 @@ public:
static char ID;
public:
- AMDGPUCFGPrepare(TargetMachine &tm AMDIL_OPT_LEVEL_DECL);
+ AMDGPUCFGPrepare(TargetMachine &tm);
virtual const char *getPassName() const;
virtual void getAnalysisUsage(AnalysisUsage &AU) const;
@@ -2687,8 +2687,8 @@ private:
char AMDGPUCFGPrepare::ID = 0;
} //end of namespace llvm
-AMDGPUCFGPrepare::AMDGPUCFGPrepare(TargetMachine &tm AMDIL_OPT_LEVEL_DECL)
- : AMDGPUCFGStructurizer(ID, tm AMDIL_OPT_LEVEL_VAR)
+AMDGPUCFGPrepare::AMDGPUCFGPrepare(TargetMachine &tm)
+ : AMDGPUCFGStructurizer(ID, tm )
{
}
const char *AMDGPUCFGPrepare::getPassName() const {
@@ -2720,7 +2720,7 @@ public:
static char ID;
public:
- AMDGPUCFGPerform(TargetMachine &tm AMDIL_OPT_LEVEL_DECL);
+ AMDGPUCFGPerform(TargetMachine &tm);
virtual const char *getPassName() const;
virtual void getAnalysisUsage(AnalysisUsage &AU) const;
bool runOnMachineFunction(MachineFunction &F);
@@ -2732,8 +2732,8 @@ private:
char AMDGPUCFGPerform::ID = 0;
} //end of namespace llvm
- AMDGPUCFGPerform::AMDGPUCFGPerform(TargetMachine &tm AMDIL_OPT_LEVEL_DECL)
-: AMDGPUCFGStructurizer(ID, tm AMDIL_OPT_LEVEL_VAR)
+ AMDGPUCFGPerform::AMDGPUCFGPerform(TargetMachine &tm)
+: AMDGPUCFGStructurizer(ID, tm)
{
}
@@ -3213,8 +3213,8 @@ struct CFGStructTraits<AMDGPUCFGStructurizer>
// createAMDGPUCFGPreparationPass- Returns a pass
FunctionPass *llvm::createAMDGPUCFGPreparationPass(TargetMachine &tm
- AMDIL_OPT_LEVEL_DECL) {
- return new AMDGPUCFGPrepare(tm AMDIL_OPT_LEVEL_VAR);
+ ) {
+ return new AMDGPUCFGPrepare(tm );
}
bool AMDGPUCFGPrepare::runOnMachineFunction(MachineFunction &func) {
@@ -3225,8 +3225,8 @@ bool AMDGPUCFGPrepare::runOnMachineFunction(MachineFunction &func) {
// createAMDGPUCFGStructurizerPass- Returns a pass
FunctionPass *llvm::createAMDGPUCFGStructurizerPass(TargetMachine &tm
- AMDIL_OPT_LEVEL_DECL) {
- return new AMDGPUCFGPerform(tm AMDIL_OPT_LEVEL_VAR);
+ ) {
+ return new AMDGPUCFGPerform(tm );
}
bool AMDGPUCFGPerform::runOnMachineFunction(MachineFunction &func) {
diff --git a/src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp b/src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp
index 0592c1209d9..58a6ed2d9d8 100644
--- a/src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp
+++ b/src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp
@@ -38,7 +38,7 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel {
// make the right decision when generating code for different targets.
const AMDGPUSubtarget &Subtarget;
public:
- AMDGPUDAGToDAGISel(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
+ AMDGPUDAGToDAGISel(TargetMachine &TM);
virtual ~AMDGPUDAGToDAGISel();
SDNode *Select(SDNode *N);
@@ -80,13 +80,13 @@ private:
// DAG, ready for instruction scheduling.
//
FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM
- AMDIL_OPT_LEVEL_DECL) {
- return new AMDGPUDAGToDAGISel(TM AMDIL_OPT_LEVEL_VAR);
+ ) {
+ return new AMDGPUDAGToDAGISel(TM);
}
AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM
- AMDIL_OPT_LEVEL_DECL)
- : SelectionDAGISel(TM AMDIL_OPT_LEVEL_VAR), Subtarget(TM.getSubtarget<AMDGPUSubtarget>())
+ )
+ : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>())
{
}
diff --git a/src/gallium/drivers/radeon/AMDILPeepholeOptimizer.cpp b/src/gallium/drivers/radeon/AMDILPeepholeOptimizer.cpp
index 4a008ddcef7..f869b332e53 100644
--- a/src/gallium/drivers/radeon/AMDILPeepholeOptimizer.cpp
+++ b/src/gallium/drivers/radeon/AMDILPeepholeOptimizer.cpp
@@ -41,7 +41,7 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUPeepholeOpt : public FunctionPass {
public:
TargetMachine &TM;
static char ID;
- AMDGPUPeepholeOpt(TargetMachine &tm AMDIL_OPT_LEVEL_DECL);
+ AMDGPUPeepholeOpt(TargetMachine &tm);
~AMDGPUPeepholeOpt();
const char *getPassName() const;
bool runOnFunction(Function &F);
@@ -153,13 +153,13 @@ Function safeNestedForEach(InputIterator First, InputIterator Last,
namespace llvm {
FunctionPass *
- createAMDGPUPeepholeOpt(TargetMachine &tm AMDIL_OPT_LEVEL_DECL)
+ createAMDGPUPeepholeOpt(TargetMachine &tm)
{
- return new AMDGPUPeepholeOpt(tm AMDIL_OPT_LEVEL_VAR);
+ return new AMDGPUPeepholeOpt(tm);
}
} // llvm namespace
-AMDGPUPeepholeOpt::AMDGPUPeepholeOpt(TargetMachine &tm AMDIL_OPT_LEVEL_DECL)
+AMDGPUPeepholeOpt::AMDGPUPeepholeOpt(TargetMachine &tm)
: FunctionPass(ID), TM(tm)
{
mDebug = false;
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-14 23:52:59 +0000