diff options
Diffstat (limited to 'src')
69 files changed, 417 insertions, 417 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index ccaab63b84b..6134749d848 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -421,7 +421,7 @@ radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer, } static void -radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va, +radv_emit_write_data_packet(struct radeon_cmdbuf *cs, uint64_t va, unsigned count, const uint32_t *data) { radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0)); @@ -436,7 +436,7 @@ radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va, void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer) { struct radv_device *device = cmd_buffer->device; - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; uint64_t va; va = radv_buffer_get_va(device->trace_bo); @@ -486,7 +486,7 @@ radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_pipeline *pipeline, enum ring_type ring) { struct radv_device *device = cmd_buffer->device; - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; uint32_t data[2]; uint64_t va; @@ -536,7 +536,7 @@ radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer, struct radv_descriptor_state *descriptors_state = radv_get_descriptors_state(cmd_buffer, bind_point); struct radv_device *device = cmd_buffer->device; - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; uint32_t data[MAX_SETS * 2] = {}; uint64_t va; unsigned i; @@ -589,7 +589,7 @@ radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer, gl_shader_stage stage) { struct radv_device *device = cmd_buffer->device; - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; uint32_t sh_base = pipeline->user_data_0[stage]; struct radv_userdata_locations *locs = &pipeline->shaders[stage]->info.user_sgprs_locs; @@ -1183,7 +1183,7 @@ radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer, { struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer; const struct radv_subpass *subpass = cmd_buffer->state.subpass; - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; struct radv_attachment_info *att; uint32_t att_idx; @@ -1223,7 +1223,7 @@ radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer, VkClearDepthStencilValue ds_clear_value, VkImageAspectFlags aspects) { - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; uint64_t va = radv_buffer_get_va(image->bo); unsigned reg_offset = 0, reg_count = 0; @@ -1262,7 +1262,7 @@ static void radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image) { - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; VkImageAspectFlags aspects = vk_format_aspects(image->vk_format); uint64_t va = radv_buffer_get_va(image->bo); unsigned reg_offset = 0, reg_count = 0; @@ -1331,7 +1331,7 @@ radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, { struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer; const struct radv_subpass *subpass = cmd_buffer->state.subpass; - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; struct radv_attachment_info *att; uint32_t att_idx; @@ -1360,7 +1360,7 @@ radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, int cb_idx, uint32_t color_values[2]) { - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; uint64_t va = radv_buffer_get_va(image->bo); va += image->offset + image->clear_value_offset; @@ -1388,7 +1388,7 @@ radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, int cb_idx) { - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; uint64_t va = radv_buffer_get_va(image->bo); va += image->offset + image->clear_value_offset; @@ -1486,7 +1486,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) static void radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer) { - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; struct radv_cmd_state *state = &cmd_buffer->state; if (state->index_type != state->last_index_type) { @@ -1850,7 +1850,7 @@ radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw, { struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info; struct radv_cmd_state *state = &cmd_buffer->state; - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; uint32_t ia_multi_vgt_param; int32_t primitive_reset_en; @@ -3087,7 +3087,7 @@ radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t count_va, uint32_t stride) { - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA : V_0287F0_DI_SRC_SEL_AUTO_INDEX; bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id; @@ -3175,7 +3175,7 @@ radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer, { struct radv_cmd_state *state = &cmd_buffer->state; struct radeon_winsys *ws = cmd_buffer->device->ws; - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; if (info->indirect) { uint64_t va = radv_buffer_get_va(info->indirect->bo); @@ -3643,7 +3643,7 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE]; unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator; struct radeon_winsys *ws = cmd_buffer->device->ws; - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; struct radv_userdata_info *loc; loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE, @@ -4202,7 +4202,7 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags stageMask, unsigned value) { - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; uint64_t va = radv_buffer_get_va(event->bo); radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8); @@ -4255,7 +4255,7 @@ void radv_CmdWaitEvents(VkCommandBuffer commandBuffer, const VkImageMemoryBarrier* pImageMemoryBarriers) { RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; for (unsigned i = 0; i < eventCount; ++i) { RADV_FROM_HANDLE(radv_event, event, pEvents[i]); diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h index 840597686a8..a5792fcc959 100644 --- a/src/amd/vulkan/radv_cs.h +++ b/src/amd/vulkan/radv_cs.h @@ -31,7 +31,7 @@ #include "sid.h" static inline unsigned radeon_check_space(struct radeon_winsys *ws, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, unsigned needed) { if (cs->max_dw - cs->cdw < needed) @@ -39,7 +39,7 @@ static inline unsigned radeon_check_space(struct radeon_winsys *ws, return cs->cdw + needed; } -static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) +static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) { assert(reg < SI_CONTEXT_REG_OFFSET); assert(cs->cdw + 2 + num <= cs->max_dw); @@ -48,13 +48,13 @@ static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsign radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2); } -static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) +static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) { radeon_set_config_reg_seq(cs, reg, 1); radeon_emit(cs, value); } -static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) +static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) { assert(reg >= SI_CONTEXT_REG_OFFSET); assert(cs->cdw + 2 + num <= cs->max_dw); @@ -63,14 +63,14 @@ static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsig radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); } -static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) +static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) { radeon_set_context_reg_seq(cs, reg, 1); radeon_emit(cs, value); } -static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs, +static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, unsigned value) { @@ -81,7 +81,7 @@ static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs, radeon_emit(cs, value); } -static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) +static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) { assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END); assert(cs->cdw + 2 + num <= cs->max_dw); @@ -90,13 +90,13 @@ static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned r radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2); } -static inline void radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) +static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) { radeon_set_sh_reg_seq(cs, reg, 1); radeon_emit(cs, value); } -static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) +static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) { assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); assert(cs->cdw + 2 + num <= cs->max_dw); @@ -105,13 +105,13 @@ static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsig radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); } -static inline void radeon_set_uconfig_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) +static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) { radeon_set_uconfig_reg_seq(cs, reg, 1); radeon_emit(cs, value); } -static inline void radeon_set_uconfig_reg_idx(struct radeon_winsys_cs *cs, +static inline void radeon_set_uconfig_reg_idx(struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, unsigned value) { diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c index 5a9b43644ed..08fc80c12ab 100644 --- a/src/amd/vulkan/radv_debug.c +++ b/src/amd/vulkan/radv_debug.c @@ -80,7 +80,7 @@ radv_init_trace(struct radv_device *device) } static void -radv_dump_trace(struct radv_device *device, struct radeon_winsys_cs *cs) +radv_dump_trace(struct radv_device *device, struct radeon_cmdbuf *cs) { const char *filename = getenv("RADV_TRACE_FILE"); FILE *f = fopen(filename, "w"); @@ -660,7 +660,7 @@ radv_gpu_hang_occured(struct radv_queue *queue, enum ring_type ring) } void -radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_winsys_cs *cs) +radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_cmdbuf *cs) { struct radv_pipeline *graphics_pipeline, *compute_pipeline; struct radv_device *device = queue->device; diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h index 1e71349509e..f1b0dc26a63 100644 --- a/src/amd/vulkan/radv_debug.h +++ b/src/amd/vulkan/radv_debug.h @@ -64,7 +64,7 @@ bool radv_init_trace(struct radv_device *device); void -radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_winsys_cs *cs); +radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_cmdbuf *cs); void radv_print_spirv(uint32_t *data, uint32_t size, FILE *fp); diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index a537415812b..cf9cf437b3d 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -1892,7 +1892,7 @@ radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buff } static void -radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_winsys_cs *cs, +radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs, struct radeon_winsys_bo *esgs_ring_bo, uint32_t esgs_ring_size, struct radeon_winsys_bo *gsvs_ring_bo, @@ -1919,7 +1919,7 @@ radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_winsys_cs *cs, } static void -radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_winsys_cs *cs, +radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs, unsigned hs_offchip_param, unsigned tf_ring_size, struct radeon_winsys_bo *tess_rings_bo) { @@ -1954,7 +1954,7 @@ radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_winsys_cs *cs } static void -radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_winsys_cs *cs, +radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs, struct radeon_winsys_bo *compute_scratch_bo) { uint64_t scratch_va; @@ -1974,7 +1974,7 @@ radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_winsys_cs *cs, static void radv_emit_global_shader_pointers(struct radv_queue *queue, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, struct radeon_winsys_bo *descriptor_bo) { uint64_t va; @@ -2019,9 +2019,9 @@ radv_get_preamble_cs(struct radv_queue *queue, uint32_t gsvs_ring_size, bool needs_tess_rings, bool needs_sample_positions, - struct radeon_winsys_cs **initial_full_flush_preamble_cs, - struct radeon_winsys_cs **initial_preamble_cs, - struct radeon_winsys_cs **continue_preamble_cs) + struct radeon_cmdbuf **initial_full_flush_preamble_cs, + struct radeon_cmdbuf **initial_preamble_cs, + struct radeon_cmdbuf **continue_preamble_cs) { struct radeon_winsys_bo *scratch_bo = NULL; struct radeon_winsys_bo *descriptor_bo = NULL; @@ -2029,7 +2029,7 @@ radv_get_preamble_cs(struct radv_queue *queue, struct radeon_winsys_bo *esgs_ring_bo = NULL; struct radeon_winsys_bo *gsvs_ring_bo = NULL; struct radeon_winsys_bo *tess_rings_bo = NULL; - struct radeon_winsys_cs *dest_cs[3] = {0}; + struct radeon_cmdbuf *dest_cs[3] = {0}; bool add_tess_rings = false, add_sample_positions = false; unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0; unsigned max_offchip_buffers; @@ -2154,7 +2154,7 @@ radv_get_preamble_cs(struct radv_queue *queue, descriptor_bo = queue->descriptor_bo; for(int i = 0; i < 3; ++i) { - struct radeon_winsys_cs *cs = NULL; + struct radeon_cmdbuf *cs = NULL; cs = queue->device->ws->cs_create(queue->device->ws, queue->queue_family_index ? RING_COMPUTE : RING_GFX); if (!cs) @@ -2467,7 +2467,7 @@ VkResult radv_QueueSubmit( uint32_t scratch_size = 0; uint32_t compute_scratch_size = 0; uint32_t esgs_ring_size = 0, gsvs_ring_size = 0; - struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL; + struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL; VkResult result; bool fence_emitted = false; bool tess_rings_needed = false; @@ -2498,7 +2498,7 @@ VkResult radv_QueueSubmit( return result; for (uint32_t i = 0; i < submitCount; i++) { - struct radeon_winsys_cs **cs_array; + struct radeon_cmdbuf **cs_array; bool do_flush = !i || pSubmits[i].pWaitDstStageMask; bool can_patch = true; uint32_t advance; @@ -2531,7 +2531,7 @@ VkResult radv_QueueSubmit( continue; } - cs_array = malloc(sizeof(struct radeon_winsys_cs *) * + cs_array = malloc(sizeof(struct radeon_cmdbuf *) * (pSubmits[i].commandBufferCount)); for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) { @@ -2547,7 +2547,7 @@ VkResult radv_QueueSubmit( } for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) { - struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs; + struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs; const struct radv_winsys_bo_list *bo_list = NULL; advance = MIN2(max_cs_submission, diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 113622bb0ce..70a8c63c926 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2493,7 +2493,7 @@ radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr } static void -radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs, +radv_pipeline_generate_binning_state(struct radeon_cmdbuf *cs, struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo) { @@ -2549,7 +2549,7 @@ radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs, static void -radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs, +radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *cs, struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo, const struct radv_graphics_pipeline_create_info *extra) @@ -2631,7 +2631,7 @@ radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs, } static void -radv_pipeline_generate_blend_state(struct radeon_winsys_cs *cs, +radv_pipeline_generate_blend_state(struct radeon_cmdbuf *cs, struct radv_pipeline *pipeline, const struct radv_blend_state *blend) { @@ -2658,7 +2658,7 @@ radv_pipeline_generate_blend_state(struct radeon_winsys_cs *cs, static void -radv_pipeline_generate_raster_state(struct radeon_winsys_cs *cs, +radv_pipeline_generate_raster_state(struct radeon_cmdbuf *cs, const VkGraphicsPipelineCreateInfo *pCreateInfo) { const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState; @@ -2699,7 +2699,7 @@ radv_pipeline_generate_raster_state(struct radeon_winsys_cs *cs, static void -radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs, +radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *cs, struct radv_pipeline *pipeline) { struct radv_multisample_state *ms = &pipeline->graphics.ms; @@ -2742,7 +2742,7 @@ radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs, } static void -radv_pipeline_generate_vgt_gs_mode(struct radeon_winsys_cs *cs, +radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *cs, const struct radv_pipeline *pipeline) { const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); @@ -2766,7 +2766,7 @@ radv_pipeline_generate_vgt_gs_mode(struct radeon_winsys_cs *cs, } static void -radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs, +radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *cs, struct radv_pipeline *pipeline, struct radv_shader_variant *shader) { @@ -2825,7 +2825,7 @@ radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs, } static void -radv_pipeline_generate_hw_es(struct radeon_winsys_cs *cs, +radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs, struct radv_pipeline *pipeline, struct radv_shader_variant *shader) { @@ -2839,7 +2839,7 @@ radv_pipeline_generate_hw_es(struct radeon_winsys_cs *cs, } static void -radv_pipeline_generate_hw_ls(struct radeon_winsys_cs *cs, +radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs, struct radv_pipeline *pipeline, struct radv_shader_variant *shader, const struct radv_tessellation_state *tess) @@ -2862,7 +2862,7 @@ radv_pipeline_generate_hw_ls(struct radeon_winsys_cs *cs, } static void -radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs, +radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs, struct radv_pipeline *pipeline, struct radv_shader_variant *shader, const struct radv_tessellation_state *tess) @@ -2888,7 +2888,7 @@ radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs, } static void -radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs *cs, +radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *cs, struct radv_pipeline *pipeline, const struct radv_tessellation_state *tess) { @@ -2908,7 +2908,7 @@ radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs *cs, } static void -radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs, +radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *cs, struct radv_pipeline *pipeline, const struct radv_tessellation_state *tess) { @@ -2941,7 +2941,7 @@ radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs, } static void -radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs, +radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *cs, struct radv_pipeline *pipeline, const struct radv_gs_state *gs_state) { @@ -3021,7 +3021,7 @@ static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade) } static void -radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs, +radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *cs, struct radv_pipeline *pipeline) { struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT]; @@ -3108,7 +3108,7 @@ radv_compute_db_shader_control(const struct radv_device *device, } static void -radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs, +radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *cs, struct radv_pipeline *pipeline) { struct radv_shader_variant *ps; @@ -3151,7 +3151,7 @@ radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs, } static void -radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs, +radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *cs, struct radv_pipeline *pipeline) { if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10) diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index cc839cf6222..cc336499c73 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -598,9 +598,9 @@ struct radv_queue { struct radeon_winsys_bo *esgs_ring_bo; struct radeon_winsys_bo *gsvs_ring_bo; struct radeon_winsys_bo *tess_rings_bo; - struct radeon_winsys_cs *initial_preamble_cs; - struct radeon_winsys_cs *initial_full_flush_preamble_cs; - struct radeon_winsys_cs *continue_preamble_cs; + struct radeon_cmdbuf *initial_preamble_cs; + struct radeon_cmdbuf *initial_full_flush_preamble_cs; + struct radeon_cmdbuf *continue_preamble_cs; }; struct radv_bo_list { @@ -621,7 +621,7 @@ struct radv_device { struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES]; int queue_count[RADV_MAX_QUEUE_FAMILIES]; - struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES]; + struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES]; bool always_use_syncobj; bool has_distributed_tess; @@ -1007,7 +1007,7 @@ struct radv_cmd_buffer { VkCommandBufferUsageFlags usage_flags; VkCommandBufferLevel level; enum radv_cmd_buffer_status status; - struct radeon_winsys_cs *cs; + struct radeon_cmdbuf *cs; struct radv_cmd_state state; struct radv_vertex_binding vertex_bindings[MAX_VBS]; uint32_t queue_family_index; @@ -1050,15 +1050,15 @@ void si_init_config(struct radv_cmd_buffer *cmd_buffer); void cik_create_gfx_config(struct radv_device *device); -void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp, +void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp, int count, const VkViewport *viewports); -void si_write_scissors(struct radeon_winsys_cs *cs, int first, +void si_write_scissors(struct radeon_cmdbuf *cs, int first, int count, const VkRect2D *scissors, const VkViewport *viewports, bool can_use_guardband); uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_draw, bool indirect_draw, uint32_t draw_vertex_count); -void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs, +void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, bool predicated, enum chip_class chip_class, bool is_mec, @@ -1068,11 +1068,11 @@ void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs, uint32_t old_fence, uint32_t new_fence); -void si_emit_wait_fence(struct radeon_winsys_cs *cs, +void si_emit_wait_fence(struct radeon_cmdbuf *cs, bool predicated, uint64_t va, uint32_t ref, uint32_t mask); -void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, +void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum chip_class chip_class, uint32_t *fence_ptr, uint64_t va, bool is_mec, @@ -1106,7 +1106,7 @@ void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer); void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer); void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer); void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer); -void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples); +void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples); unsigned radv_cayman_get_maxdist(int log_samples); void radv_device_init_msaa(struct radv_device *device); @@ -1132,7 +1132,7 @@ bool radv_get_memory_fd(struct radv_device *device, int *pFD); static inline void -radv_emit_shader_pointer_head(struct radeon_winsys_cs *cs, +radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs, unsigned sh_offset, unsigned pointer_count, bool use_32bit_pointers) { @@ -1142,7 +1142,7 @@ radv_emit_shader_pointer_head(struct radeon_winsys_cs *cs, static inline void radv_emit_shader_pointer_body(struct radv_device *device, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, uint64_t va, bool use_32bit_pointers) { radeon_emit(cs, va); @@ -1157,7 +1157,7 @@ radv_emit_shader_pointer_body(struct radv_device *device, static inline void radv_emit_shader_pointer(struct radv_device *device, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, uint32_t sh_offset, uint64_t va, bool global) { bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global; @@ -1272,7 +1272,7 @@ struct radv_pipeline { struct radv_shader_variant *gs_copy_shader; VkShaderStageFlags active_stages; - struct radeon_winsys_cs cs; + struct radeon_cmdbuf cs; struct radv_vertex_elements_info vertex_elements; diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index f30796446d9..559b7cd49dc 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -950,7 +950,7 @@ void radv_CmdCopyQueryPoolResults( RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); RADV_FROM_HANDLE(radv_query_pool, pool, queryPool); RADV_FROM_HANDLE(radv_buffer, dst_buffer, dstBuffer); - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; unsigned elem_size = (flags & VK_QUERY_RESULT_64_BIT) ? 8 : 4; uint64_t va = radv_buffer_get_va(pool->bo); uint64_t dest_va = radv_buffer_get_va(dst_buffer->bo); @@ -1082,7 +1082,7 @@ static void emit_begin_query(struct radv_cmd_buffer *cmd_buffer, VkQueryType query_type, VkQueryControlFlags flags) { - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; switch (query_type) { case VK_QUERY_TYPE_OCCLUSION: radeon_check_space(cmd_buffer->device->ws, cs, 7); @@ -1133,7 +1133,7 @@ static void emit_end_query(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint64_t avail_va, VkQueryType query_type) { - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; switch (query_type) { case VK_QUERY_TYPE_OCCLUSION: radeon_check_space(cmd_buffer->device->ws, cs, 14); @@ -1184,7 +1184,7 @@ void radv_CmdBeginQuery( { RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); RADV_FROM_HANDLE(radv_query_pool, pool, queryPool); - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; uint64_t va = radv_buffer_get_va(pool->bo); radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo, 8); @@ -1253,7 +1253,7 @@ void radv_CmdWriteTimestamp( RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); RADV_FROM_HANDLE(radv_query_pool, pool, queryPool); bool mec = radv_cmd_buffer_uses_mec(cmd_buffer); - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; uint64_t va = radv_buffer_get_va(pool->bo); uint64_t avail_va = va + pool->availability_offset + 4 * query; uint64_t query_va = va + pool->stride * query; diff --git a/src/amd/vulkan/radv_radeon_winsys.h b/src/amd/vulkan/radv_radeon_winsys.h index 2ebd18cf905..8b723e9fb88 100644 --- a/src/amd/vulkan/radv_radeon_winsys.h +++ b/src/amd/vulkan/radv_radeon_winsys.h @@ -96,7 +96,7 @@ enum radeon_value_id { RADEON_CURRENT_MCLK, }; -struct radeon_winsys_cs { +struct radeon_cmdbuf { unsigned cdw; /* Number of used dwords. */ unsigned max_dw; /* Maximum number of dwords. */ uint32_t *buf; /* The base pointer of the chunk. */ @@ -234,36 +234,36 @@ struct radeon_winsys { bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx, enum ring_type ring_type, int ring_index); - struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys *ws, + struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws, enum ring_type ring_type); - void (*cs_destroy)(struct radeon_winsys_cs *cs); + void (*cs_destroy)(struct radeon_cmdbuf *cs); - void (*cs_reset)(struct radeon_winsys_cs *cs); + void (*cs_reset)(struct radeon_cmdbuf *cs); - bool (*cs_finalize)(struct radeon_winsys_cs *cs); + bool (*cs_finalize)(struct radeon_cmdbuf *cs); - void (*cs_grow)(struct radeon_winsys_cs * cs, size_t min_size); + void (*cs_grow)(struct radeon_cmdbuf * cs, size_t min_size); int (*cs_submit)(struct radeon_winsys_ctx *ctx, int queue_index, - struct radeon_winsys_cs **cs_array, + struct radeon_cmdbuf **cs_array, unsigned cs_count, - struct radeon_winsys_cs *initial_preamble_cs, - struct radeon_winsys_cs *continue_preamble_cs, + struct radeon_cmdbuf *initial_preamble_cs, + struct radeon_cmdbuf *continue_preamble_cs, struct radv_winsys_sem_info *sem_info, const struct radv_winsys_bo_list *bo_list, /* optional */ bool can_patch, struct radeon_winsys_fence *fence); - void (*cs_add_buffer)(struct radeon_winsys_cs *cs, + void (*cs_add_buffer)(struct radeon_cmdbuf *cs, struct radeon_winsys_bo *bo, uint8_t priority); - void (*cs_execute_secondary)(struct radeon_winsys_cs *parent, - struct radeon_winsys_cs *child); + void (*cs_execute_secondary)(struct radeon_cmdbuf *parent, + struct radeon_cmdbuf *child); - void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, const int *trace_ids, int trace_id_count); + void (*cs_dump)(struct radeon_cmdbuf *cs, FILE* file, const int *trace_ids, int trace_id_count); int (*surface_init)(struct radeon_winsys *ws, const struct ac_surf_info *surf_info, @@ -307,12 +307,12 @@ struct radeon_winsys { }; -static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value) +static inline void radeon_emit(struct radeon_cmdbuf *cs, uint32_t value) { cs->buf[cs->cdw++] = value; } -static inline void radeon_emit_array(struct radeon_winsys_cs *cs, +static inline void radeon_emit_array(struct radeon_cmdbuf *cs, const uint32_t *values, unsigned count) { memcpy(cs->buf + cs->cdw, values, count * 4); @@ -325,7 +325,7 @@ static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo *bo) } static inline void radv_cs_add_buffer(struct radeon_winsys *ws, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, struct radeon_winsys_bo *bo, uint8_t priority) { diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 4c3a888f3cf..0692124bf51 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -37,7 +37,7 @@ static void si_write_harvested_raster_configs(struct radv_physical_device *physical_device, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, unsigned raster_config, unsigned raster_config_1) { @@ -81,7 +81,7 @@ si_write_harvested_raster_configs(struct radv_physical_device *physical_device, static void si_emit_compute(struct radv_physical_device *physical_device, - struct radeon_winsys_cs *cs) + struct radeon_cmdbuf *cs) { radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3); radeon_emit(cs, 0); @@ -135,7 +135,7 @@ static unsigned radv_pack_float_12p4(float x) static void si_set_raster_config(struct radv_physical_device *physical_device, - struct radeon_winsys_cs *cs) + struct radeon_cmdbuf *cs) { unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16); unsigned rb_mask = physical_device->rad_info.enabled_rb_mask; @@ -163,7 +163,7 @@ si_set_raster_config(struct radv_physical_device *physical_device, static void si_emit_config(struct radv_physical_device *physical_device, - struct radeon_winsys_cs *cs) + struct radeon_cmdbuf *cs) { int i; @@ -399,7 +399,7 @@ void si_init_config(struct radv_cmd_buffer *cmd_buffer) void cik_create_gfx_config(struct radv_device *device) { - struct radeon_winsys_cs *cs = device->ws->cs_create(device->ws, RING_GFX); + struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX); if (!cs) return; @@ -456,7 +456,7 @@ get_viewport_xform(const VkViewport *viewport, } void -si_write_viewport(struct radeon_winsys_cs *cs, int first_vp, +si_write_viewport(struct radeon_cmdbuf *cs, int first_vp, int count, const VkViewport *viewports) { int i; @@ -515,7 +515,7 @@ static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) { } void -si_write_scissors(struct radeon_winsys_cs *cs, int first, +si_write_scissors(struct radeon_cmdbuf *cs, int first, int count, const VkRect2D *scissors, const VkViewport *viewports, bool can_use_guardband) { @@ -672,7 +672,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, } -void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs, +void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, bool predicated, enum chip_class chip_class, bool is_mec, @@ -722,7 +722,7 @@ void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs, } void -si_emit_wait_fence(struct radeon_winsys_cs *cs, +si_emit_wait_fence(struct radeon_cmdbuf *cs, bool predicated, uint64_t va, uint32_t ref, uint32_t mask) @@ -737,7 +737,7 @@ si_emit_wait_fence(struct radeon_winsys_cs *cs, } static void -si_emit_acquire_mem(struct radeon_winsys_cs *cs, +si_emit_acquire_mem(struct radeon_cmdbuf *cs, bool is_mec, bool predicated, bool is_gfx9, @@ -764,7 +764,7 @@ si_emit_acquire_mem(struct radeon_winsys_cs *cs, } void -si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, +si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum chip_class chip_class, uint32_t *flush_cnt, uint64_t flush_va, @@ -1039,7 +1039,7 @@ static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer, uint64_t dst_va, uint64_t src_va, unsigned size, unsigned flags) { - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; uint32_t header = 0, command = 0; assert(size); @@ -1317,7 +1317,7 @@ unsigned radv_cayman_get_maxdist(int log_samples) return max_dist[log_samples]; } -void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples) +void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples) { switch (nr_samples) { default: diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c index 0cd870b7c89..848e81924ff 100644 --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c @@ -41,7 +41,7 @@ enum { }; struct radv_amdgpu_cs { - struct radeon_winsys_cs base; + struct radeon_cmdbuf base; struct radv_amdgpu_winsys *ws; struct amdgpu_cs_ib_info ib; @@ -70,12 +70,12 @@ struct radv_amdgpu_cs { int *virtual_buffer_hash_table; /* For chips that don't support chaining. */ - struct radeon_winsys_cs *old_cs_buffers; + struct radeon_cmdbuf *old_cs_buffers; unsigned num_old_cs_buffers; }; static inline struct radv_amdgpu_cs * -radv_amdgpu_cs(struct radeon_winsys_cs *base) +radv_amdgpu_cs(struct radeon_cmdbuf *base) { return (struct radv_amdgpu_cs*)base; } @@ -193,7 +193,7 @@ static bool radv_amdgpu_fences_wait(struct radeon_winsys *_ws, return false; } -static void radv_amdgpu_cs_destroy(struct radeon_winsys_cs *rcs) +static void radv_amdgpu_cs_destroy(struct radeon_cmdbuf *rcs) { struct radv_amdgpu_cs *cs = radv_amdgpu_cs(rcs); @@ -206,7 +206,7 @@ static void radv_amdgpu_cs_destroy(struct radeon_winsys_cs *rcs) cs->ws->base.buffer_destroy(cs->old_ib_buffers[i]); for (unsigned i = 0; i < cs->num_old_cs_buffers; ++i) { - struct radeon_winsys_cs *rcs = &cs->old_cs_buffers[i]; + struct radeon_cmdbuf *rcs = &cs->old_cs_buffers[i]; free(rcs->buf); } @@ -229,7 +229,7 @@ static void radv_amdgpu_init_cs(struct radv_amdgpu_cs *cs, cs->hw_ip = ring_to_hw_ip(ring_type); } -static struct radeon_winsys_cs * +static struct radeon_cmdbuf * radv_amdgpu_cs_create(struct radeon_winsys *ws, enum ring_type ring_type) { @@ -279,7 +279,7 @@ radv_amdgpu_cs_create(struct radeon_winsys *ws, return &cs->base; } -static void radv_amdgpu_cs_grow(struct radeon_winsys_cs *_cs, size_t min_size) +static void radv_amdgpu_cs_grow(struct radeon_cmdbuf *_cs, size_t min_size) { struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs); @@ -401,7 +401,7 @@ static void radv_amdgpu_cs_grow(struct radeon_winsys_cs *_cs, size_t min_size) } -static bool radv_amdgpu_cs_finalize(struct radeon_winsys_cs *_cs) +static bool radv_amdgpu_cs_finalize(struct radeon_cmdbuf *_cs) { struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs); @@ -417,7 +417,7 @@ static bool radv_amdgpu_cs_finalize(struct radeon_winsys_cs *_cs) return !cs->failed; } -static void radv_amdgpu_cs_reset(struct radeon_winsys_cs *_cs) +static void radv_amdgpu_cs_reset(struct radeon_cmdbuf *_cs) { struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs); cs->base.cdw = 0; @@ -449,7 +449,7 @@ static void radv_amdgpu_cs_reset(struct radeon_winsys_cs *_cs) cs->ib.size = 0; } else { for (unsigned i = 0; i < cs->num_old_cs_buffers; ++i) { - struct radeon_winsys_cs *rcs = &cs->old_cs_buffers[i]; + struct radeon_cmdbuf *rcs = &cs->old_cs_buffers[i]; free(rcs->buf); } @@ -509,7 +509,7 @@ static void radv_amdgpu_cs_add_buffer_internal(struct radv_amdgpu_cs *cs, ++cs->num_buffers; } -static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_winsys_cs *_cs, +static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_cmdbuf *_cs, struct radeon_winsys_bo *bo, uint8_t priority) { @@ -552,7 +552,7 @@ static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_winsys_cs *_cs, } -static void radv_amdgpu_cs_add_buffer(struct radeon_winsys_cs *_cs, +static void radv_amdgpu_cs_add_buffer(struct radeon_cmdbuf *_cs, struct radeon_winsys_bo *_bo, uint8_t priority) { @@ -570,8 +570,8 @@ static void radv_amdgpu_cs_add_buffer(struct radeon_winsys_cs *_cs, radv_amdgpu_cs_add_buffer_internal(cs, bo->bo, priority); } -static void radv_amdgpu_cs_execute_secondary(struct radeon_winsys_cs *_parent, - struct radeon_winsys_cs *_child) +static void radv_amdgpu_cs_execute_secondary(struct radeon_cmdbuf *_parent, + struct radeon_cmdbuf *_child) { struct radv_amdgpu_cs *parent = radv_amdgpu_cs(_parent); struct radv_amdgpu_cs *child = radv_amdgpu_cs(_child); @@ -604,11 +604,11 @@ static void radv_amdgpu_cs_execute_secondary(struct radeon_winsys_cs *_parent, } static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws, - struct radeon_winsys_cs **cs_array, + struct radeon_cmdbuf **cs_array, unsigned count, struct radv_amdgpu_winsys_bo **extra_bo_array, unsigned num_extra_bo, - struct radeon_winsys_cs *extra_cs, + struct radeon_cmdbuf *extra_cs, const struct radv_winsys_bo_list *radv_bo_list, amdgpu_bo_list_handle *bo_list) { @@ -794,10 +794,10 @@ static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx, int queue_idx, struct radv_winsys_sem_info *sem_info, const struct radv_winsys_bo_list *radv_bo_list, - struct radeon_winsys_cs **cs_array, + struct radeon_cmdbuf **cs_array, unsigned cs_count, - struct radeon_winsys_cs *initial_preamble_cs, - struct radeon_winsys_cs *continue_preamble_cs, + struct radeon_cmdbuf *initial_preamble_cs, + struct radeon_cmdbuf *continue_preamble_cs, struct radeon_winsys_fence *_fence) { int r; @@ -876,10 +876,10 @@ static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx, int queue_idx, struct radv_winsys_sem_info *sem_info, const struct radv_winsys_bo_list *radv_bo_list, - struct radeon_winsys_cs **cs_array, + struct radeon_cmdbuf **cs_array, unsigned cs_count, - struct radeon_winsys_cs *initial_preamble_cs, - struct radeon_winsys_cs *continue_preamble_cs, + struct radeon_cmdbuf *initial_preamble_cs, + struct radeon_cmdbuf *continue_preamble_cs, struct radeon_winsys_fence *_fence) { int r; @@ -893,7 +893,7 @@ static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx, for (unsigned i = 0; i < cs_count;) { struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[i]); struct amdgpu_cs_ib_info ibs[AMDGPU_CS_MAX_IBS_PER_SUBMIT]; - struct radeon_winsys_cs *preamble_cs = i ? continue_preamble_cs : initial_preamble_cs; + struct radeon_cmdbuf *preamble_cs = i ? continue_preamble_cs : initial_preamble_cs; unsigned cnt = MIN2(AMDGPU_CS_MAX_IBS_PER_SUBMIT - !!preamble_cs, cs_count - i); @@ -958,10 +958,10 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx, int queue_idx, struct radv_winsys_sem_info *sem_info, const struct radv_winsys_bo_list *radv_bo_list, - struct radeon_winsys_cs **cs_array, + struct radeon_cmdbuf **cs_array, unsigned cs_count, - struct radeon_winsys_cs *initial_preamble_cs, - struct radeon_winsys_cs *continue_preamble_cs, + struct radeon_cmdbuf *initial_preamble_cs, + struct radeon_cmdbuf *continue_preamble_cs, struct radeon_winsys_fence *_fence) { int r; @@ -983,7 +983,7 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx, struct amdgpu_cs_ib_info ibs[AMDGPU_CS_MAX_IBS_PER_SUBMIT] = {0}; unsigned number_of_ibs = 1; struct radeon_winsys_bo *bos[AMDGPU_CS_MAX_IBS_PER_SUBMIT] = {0}; - struct radeon_winsys_cs *preamble_cs = i ? continue_preamble_cs : initial_preamble_cs; + struct radeon_cmdbuf *preamble_cs = i ? continue_preamble_cs : initial_preamble_cs; struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]); uint32_t *ptr; unsigned cnt = 0; @@ -996,7 +996,7 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx, * IB per submit. */ unsigned new_cs_count = cs->num_old_cs_buffers + 1; - struct radeon_winsys_cs *new_cs_array[AMDGPU_CS_MAX_IBS_PER_SUBMIT]; + struct radeon_cmdbuf *new_cs_array[AMDGPU_CS_MAX_IBS_PER_SUBMIT]; unsigned idx = 0; for (unsigned j = 0; j < cs->num_old_cs_buffers; j++) @@ -1004,7 +1004,7 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx, new_cs_array[idx++] = cs_array[i]; for (unsigned j = 0; j < new_cs_count; j++) { - struct radeon_winsys_cs *rcs = new_cs_array[j]; + struct radeon_cmdbuf *rcs = new_cs_array[j]; bool needs_preamble = preamble_cs && j == 0; unsigned size = 0; @@ -1134,10 +1134,10 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx, static int radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx, int queue_idx, - struct radeon_winsys_cs **cs_array, + struct radeon_cmdbuf **cs_array, unsigned cs_count, - struct radeon_winsys_cs *initial_preamble_cs, - struct radeon_winsys_cs *continue_preamble_cs, + struct radeon_cmdbuf *initial_preamble_cs, + struct radeon_cmdbuf *continue_preamble_cs, struct radv_winsys_sem_info *sem_info, const struct radv_winsys_bo_list *bo_list, bool can_patch, @@ -1196,7 +1196,7 @@ static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs, uint64_t addr) return ret; } -static void radv_amdgpu_winsys_cs_dump(struct radeon_winsys_cs *_cs, +static void radv_amdgpu_winsys_cs_dump(struct radeon_cmdbuf *_cs, FILE* file, const int *trace_ids, int trace_id_count) { diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index 22025157764..667d3fd3306 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -449,7 +449,7 @@ struct r300_context { /* The submission context. */ struct radeon_winsys_ctx *ctx; /* The command stream. */ - struct radeon_winsys_cs *cs; + struct radeon_cmdbuf *cs; /* Screen. */ struct r300_screen *screen; diff --git a/src/gallium/drivers/r300/r300_cs.h b/src/gallium/drivers/r300/r300_cs.h index 727b9e22475..560b77533cf 100644 --- a/src/gallium/drivers/r300/r300_cs.h +++ b/src/gallium/drivers/r300/r300_cs.h @@ -39,7 +39,7 @@ */ #define CS_LOCALS(context) \ - struct radeon_winsys_cs *cs_copy = (context)->cs; \ + struct radeon_cmdbuf *cs_copy = (context)->cs; \ struct radeon_winsys *cs_winsys = (context)->rws; \ int cs_count = 0; (void) cs_count; (void) cs_winsys; diff --git a/src/gallium/drivers/r600/cayman_msaa.c b/src/gallium/drivers/r600/cayman_msaa.c index f97924ac22c..e349cdb9e11 100644 --- a/src/gallium/drivers/r600/cayman_msaa.c +++ b/src/gallium/drivers/r600/cayman_msaa.c @@ -141,7 +141,7 @@ void cayman_init_msaa(struct pipe_context *ctx) cayman_get_sample_position(ctx, 16, i, rctx->sample_locations_16x[i]); } -static void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples) +static void cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples) { switch (nr_samples) { default: @@ -202,7 +202,7 @@ static void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_sam } } -void cayman_emit_msaa_state(struct radeon_winsys_cs *cs, int nr_samples, +void cayman_emit_msaa_state(struct radeon_cmdbuf *cs, int nr_samples, int ps_iter_samples, int overrast_samples) { int setup_samples = nr_samples > 1 ? nr_samples : diff --git a/src/gallium/drivers/r600/evergreen_compute.c b/src/gallium/drivers/r600/evergreen_compute.c index 8c818700b6c..90eae1e2829 100644 --- a/src/gallium/drivers/r600/evergreen_compute.c +++ b/src/gallium/drivers/r600/evergreen_compute.c @@ -575,7 +575,7 @@ static void evergreen_emit_dispatch(struct r600_context *rctx, uint32_t indirect_grid[3]) { int i; - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_pipe_compute *shader = rctx->cs_shader_state.shader; bool render_cond_bit = rctx->b.render_cond && !rctx->b.render_cond_force_off; unsigned num_waves; @@ -654,7 +654,7 @@ static void evergreen_emit_dispatch(struct r600_context *rctx, static void compute_setup_cbs(struct r600_context *rctx) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; unsigned i; /* Emit colorbuffers. */ @@ -696,7 +696,7 @@ static void compute_setup_cbs(struct r600_context *rctx) static void compute_emit_cs(struct r600_context *rctx, const struct pipe_grid_info *info) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; bool compute_dirty = false; struct r600_pipe_shader *current; struct r600_shader_atomic combined_atomics[8]; @@ -853,7 +853,7 @@ void evergreen_emit_cs_shader(struct r600_context *rctx, struct r600_cs_shader_state *state = (struct r600_cs_shader_state*)atom; struct r600_pipe_compute *shader = state->shader; - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; uint64_t va; struct r600_resource *code_bo; unsigned ngpr, nstack; diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c index 5352dc05779..2484d5ba6e6 100644 --- a/src/gallium/drivers/r600/evergreen_hw_context.c +++ b/src/gallium/drivers/r600/evergreen_hw_context.c @@ -35,7 +35,7 @@ void evergreen_dma_copy_buffer(struct r600_context *rctx, uint64_t src_offset, uint64_t size) { - struct radeon_winsys_cs *cs = rctx->b.dma.cs; + struct radeon_cmdbuf *cs = rctx->b.dma.cs; unsigned i, ncopy, csize, sub_cmd, shift; struct r600_resource *rdst = (struct r600_resource*)dst; struct r600_resource *rsrc = (struct r600_resource*)src; @@ -87,7 +87,7 @@ void evergreen_cp_dma_clear_buffer(struct r600_context *rctx, unsigned size, uint32_t clear_value, enum r600_coherency coher) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; assert(size); assert(rctx->screen->b.has_cp_dma); diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 05f4a65059b..a484f0078aa 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -965,7 +965,7 @@ evergreen_create_sampler_view(struct pipe_context *ctx, static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_config_state *a = (struct r600_config_state*)atom; radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3); @@ -992,7 +992,7 @@ static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_a static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct pipe_clip_state *state = &rctx->clip_state.state; radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4); @@ -1648,7 +1648,7 @@ static void evergreen_get_sample_position(struct pipe_context *ctx, static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; unsigned max_dist = 0; switch (nr_samples) { @@ -1697,7 +1697,7 @@ static void evergreen_emit_image_state(struct r600_context *rctx, struct r600_at { struct r600_image_state *state = (struct r600_image_state *)atom; struct pipe_framebuffer_state *fb_state = &rctx->framebuffer.state; - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_texture *rtex; struct r600_resource *resource; int i; @@ -1824,7 +1824,7 @@ static void evergreen_emit_compute_buffer_state(struct r600_context *rctx, struc static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct pipe_framebuffer_state *state = &rctx->framebuffer.state; unsigned nr_cbufs = state->nr_cbufs; unsigned i, tl, br; @@ -1963,7 +1963,7 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a; float offset_units = state->offset_units; float offset_scale = state->offset_scale; @@ -2021,7 +2021,7 @@ uint32_t evergreen_construct_rat_mask(struct r600_context *rctx, struct r600_cb_ static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom; unsigned fb_colormask = a->bound_cbufs_target_mask; unsigned ps_colormask = a->ps_color_export_mask; @@ -2036,7 +2036,7 @@ static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_ static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_db_state *a = (struct r600_db_state*)atom; if (a->rsurf && a->rsurf->db_htile_surface) { @@ -2059,7 +2059,7 @@ static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom; unsigned db_render_control = 0; unsigned db_count_control = 0; @@ -2114,7 +2114,7 @@ static void evergreen_emit_vertex_buffers(struct r600_context *rctx, unsigned resource_offset, unsigned pkt_flags) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; uint32_t dirty_mask = state->dirty_mask; while (dirty_mask) { @@ -2173,7 +2173,7 @@ static void evergreen_emit_constant_buffers(struct r600_context *rctx, unsigned reg_alu_const_cache, unsigned pkt_flags) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; uint32_t dirty_mask = state->dirty_mask; while (dirty_mask) { @@ -2325,7 +2325,7 @@ static void evergreen_emit_sampler_views(struct r600_context *rctx, struct r600_samplerview_state *state, unsigned resource_id_base, unsigned pkt_flags) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; uint32_t dirty_mask = state->dirty_mask; while (dirty_mask) { @@ -2403,7 +2403,7 @@ static void evergreen_emit_sampler_states(struct r600_context *rctx, unsigned border_index_reg, unsigned pkt_flags) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; uint32_t dirty_mask = texinfo->states.dirty_mask; while (dirty_mask) { @@ -2482,7 +2482,7 @@ static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_at static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a) { struct r600_sample_mask *s = (struct r600_sample_mask*)a; - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; uint16_t mask = s->sample_mask; radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2); @@ -2492,7 +2492,7 @@ static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_cso_state *state = (struct r600_cso_state*)a; struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso; @@ -2509,7 +2509,7 @@ static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a; uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0; @@ -2613,7 +2613,7 @@ static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_ static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a; struct r600_resource *rbuffer; @@ -3716,7 +3716,7 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx, unsigned pitch, unsigned bpp) { - struct radeon_winsys_cs *cs = rctx->b.dma.cs; + struct radeon_cmdbuf *cs = rctx->b.dma.cs; struct r600_texture *rsrc = (struct r600_texture*)src; struct r600_texture *rdst = (struct r600_texture*)dst; unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size; @@ -4557,14 +4557,14 @@ uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx, } void evergreen_set_ls_hs_config(struct r600_context *rctx, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, uint32_t ls_hs_config) { radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config); } void evergreen_set_lds_alloc(struct r600_context *rctx, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, uint32_t lds_alloc) { radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc); @@ -4693,7 +4693,7 @@ bool evergreen_adjust_gprs(struct r600_context *rctx) void eg_trace_emit(struct r600_context *rctx) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; unsigned reloc; if (rctx->b.chip_class < EVERGREEN) @@ -4723,7 +4723,7 @@ static void evergreen_emit_set_append_cnt(struct r600_context *rctx, struct r600_resource *resource, uint32_t pkt_flags) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, resource, RADEON_USAGE_READ, @@ -4746,7 +4746,7 @@ static void evergreen_emit_event_write_eos(struct r600_context *rctx, struct r600_resource *resource, uint32_t pkt_flags) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; uint32_t event = EVENT_TYPE_PS_DONE; uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0; uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, @@ -4773,7 +4773,7 @@ static void cayman_emit_event_write_eos(struct r600_context *rctx, struct r600_resource *resource, uint32_t pkt_flags) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; uint32_t event = EVENT_TYPE_PS_DONE; uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, resource, @@ -4799,7 +4799,7 @@ static void cayman_write_count_to_gds(struct r600_context *rctx, struct r600_resource *resource, uint32_t pkt_flags) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, resource, RADEON_USAGE_READ, @@ -4884,7 +4884,7 @@ void evergreen_emit_atomic_buffer_save(struct r600_context *rctx, struct r600_shader_atomic *combined_atomics, uint8_t *atomic_used_mask_p) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state; uint32_t pkt_flags = 0; uint32_t event = EVENT_TYPE_PS_DONE; diff --git a/src/gallium/drivers/r600/r600_cs.h b/src/gallium/drivers/r600/r600_cs.h index 632c7f5f944..424adba2782 100644 --- a/src/gallium/drivers/r600/r600_cs.h +++ b/src/gallium/drivers/r600/r600_cs.h @@ -42,7 +42,7 @@ */ static inline bool radeon_cs_memory_below_limit(struct r600_common_screen *screen, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, uint64_t vram, uint64_t gtt) { vram += cs->used_vram; @@ -118,7 +118,7 @@ static inline void r600_emit_reloc(struct r600_common_context *rctx, enum radeon_bo_usage usage, enum radeon_bo_priority priority) { - struct radeon_winsys_cs *cs = ring->cs; + struct radeon_cmdbuf *cs = ring->cs; bool has_vm = ((struct r600_common_screen*)rctx->b.screen)->info.r600_has_virtual_memory; unsigned reloc = radeon_add_to_buffer_list(rctx, ring, rbo, usage, priority); @@ -128,7 +128,7 @@ static inline void r600_emit_reloc(struct r600_common_context *rctx, } } -static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) +static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) { assert(reg < R600_CONTEXT_REG_OFFSET); assert(cs->current.cdw + 2 + num <= cs->current.max_dw); @@ -136,13 +136,13 @@ static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsign radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2); } -static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) +static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) { radeon_set_config_reg_seq(cs, reg, 1); radeon_emit(cs, value); } -static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) +static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) { assert(reg >= R600_CONTEXT_REG_OFFSET); assert(cs->current.cdw + 2 + num <= cs->current.max_dw); @@ -150,13 +150,13 @@ static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsig radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2); } -static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) +static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) { radeon_set_context_reg_seq(cs, reg, 1); radeon_emit(cs, value); } -static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs, +static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, unsigned value) { @@ -167,7 +167,7 @@ static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs, radeon_emit(cs, value); } -static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) +static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) { assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END); assert(cs->current.cdw + 2 + num <= cs->current.max_dw); @@ -175,13 +175,13 @@ static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned r radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2); } -static inline void radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) +static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) { radeon_set_sh_reg_seq(cs, reg, 1); radeon_emit(cs, value); } -static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) +static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) { assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); assert(cs->current.cdw + 2 + num <= cs->current.max_dw); @@ -189,13 +189,13 @@ static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsig radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); } -static inline void radeon_set_uconfig_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) +static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) { radeon_set_uconfig_reg_seq(cs, reg, 1); radeon_emit(cs, value); } -static inline void radeon_set_uconfig_reg_idx(struct radeon_winsys_cs *cs, +static inline void radeon_set_uconfig_reg_idx(struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, unsigned value) { diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c index 3ce18251044..17d60b188dd 100644 --- a/src/gallium/drivers/r600/r600_hw_context.c +++ b/src/gallium/drivers/r600/r600_hw_context.c @@ -88,7 +88,7 @@ void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, void r600_flush_emit(struct r600_context *rctx) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; unsigned cp_coher_cntl = 0; unsigned wait_until = 0; @@ -257,7 +257,7 @@ void r600_context_gfx_flush(void *context, unsigned flags, struct pipe_fence_handle **fence) { struct r600_context *ctx = context; - struct radeon_winsys_cs *cs = ctx->b.gfx.cs; + struct radeon_cmdbuf *cs = ctx->b.gfx.cs; struct radeon_winsys *ws = ctx->b.ws; if (!radeon_emitted(cs, ctx->b.initial_gfx_cs_size)) @@ -433,7 +433,7 @@ void r600_begin_new_cs(struct r600_context *ctx) void r600_emit_pfp_sync_me(struct r600_context *rctx) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; if (rctx->b.chip_class >= EVERGREEN && rctx->b.screen->info.drm_minor >= 46) { @@ -499,7 +499,7 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx, struct pipe_resource *src, uint64_t src_offset, unsigned size) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; assert(size); assert(rctx->screen->b.has_cp_dma); @@ -581,7 +581,7 @@ void r600_dma_copy_buffer(struct r600_context *rctx, uint64_t src_offset, uint64_t size) { - struct radeon_winsys_cs *cs = rctx->b.dma.cs; + struct radeon_cmdbuf *cs = rctx->b.dma.cs; unsigned i, ncopy, csize; struct r600_resource *rdst = (struct r600_resource*)dst; struct r600_resource *rsrc = (struct r600_resource*)src; diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index 6d090930522..99be2f9ce66 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -616,7 +616,7 @@ struct r600_context { uint32_t append_fence_id; }; -static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs, +static inline void r600_emit_command_buffer(struct radeon_cmdbuf *cs, struct r600_command_buffer *cb) { assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw); @@ -804,10 +804,10 @@ uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned num_patches); void evergreen_set_ls_hs_config(struct r600_context *rctx, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, uint32_t ls_hs_config); void evergreen_set_lds_alloc(struct r600_context *rctx, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, uint32_t lds_alloc); /* r600_state_common.c */ @@ -980,14 +980,14 @@ static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw); void r600_release_command_buffer(struct r600_command_buffer *cb); -static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) +static inline void radeon_compute_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) { radeon_set_context_reg_seq(cs, reg, num); /* Set the compute bit on the packet header */ cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE; } -static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) +static inline void radeon_set_ctl_const_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) { assert(reg >= R600_CTL_CONST_OFFSET); assert(cs->current.cdw + 2 + num <= cs->current.max_dw); @@ -995,13 +995,13 @@ static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigne radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2); } -static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) +static inline void radeon_compute_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) { radeon_compute_set_context_reg_seq(cs, reg, 1); radeon_emit(cs, value); } -static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag) +static inline void radeon_set_context_reg_flag(struct radeon_cmdbuf *cs, unsigned reg, unsigned value, unsigned flag) { if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) { radeon_compute_set_context_reg(cs, reg, value); @@ -1010,7 +1010,7 @@ static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsi } } -static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) +static inline void radeon_set_ctl_const(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) { radeon_set_ctl_const_seq(cs, reg, 1); radeon_emit(cs, value); diff --git a/src/gallium/drivers/r600/r600_pipe_common.c b/src/gallium/drivers/r600/r600_pipe_common.c index e1d899b0fe0..85e95ee79ea 100644 --- a/src/gallium/drivers/r600/r600_pipe_common.c +++ b/src/gallium/drivers/r600/r600_pipe_common.c @@ -105,7 +105,7 @@ void r600_gfx_write_event_eop(struct r600_common_context *ctx, struct r600_resource *buf, uint64_t va, uint32_t new_fence, unsigned query_type) { - struct radeon_winsys_cs *cs = ctx->gfx.cs; + struct radeon_cmdbuf *cs = ctx->gfx.cs; unsigned op = EVENT_TYPE(event) | EVENT_INDEX(5) | event_flags; @@ -137,7 +137,7 @@ void r600_gfx_wait_fence(struct r600_common_context *ctx, struct r600_resource *buf, uint64_t va, uint32_t ref, uint32_t mask) { - struct radeon_winsys_cs *cs = ctx->gfx.cs; + struct radeon_cmdbuf *cs = ctx->gfx.cs; radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1)); @@ -242,7 +242,7 @@ void r600_draw_rectangle(struct blitter_context *blitter, static void r600_dma_emit_wait_idle(struct r600_common_context *rctx) { - struct radeon_winsys_cs *cs = rctx->dma.cs; + struct radeon_cmdbuf *cs = rctx->dma.cs; if (rctx->chip_class >= EVERGREEN) radeon_emit(cs, 0xf0000000); /* NOP */ @@ -468,7 +468,7 @@ static void r600_flush_dma_ring(void *ctx, unsigned flags, struct pipe_fence_handle **fence) { struct r600_common_context *rctx = (struct r600_common_context *)ctx; - struct radeon_winsys_cs *cs = rctx->dma.cs; + struct radeon_cmdbuf *cs = rctx->dma.cs; struct radeon_saved_cs saved; bool check_vm = (rctx->screen->debug_flags & DBG_CHECK_VM) && @@ -502,7 +502,7 @@ static void r600_flush_dma_ring(void *ctx, unsigned flags, * Store a linearized copy of all chunks of \p cs together with the buffer * list in \p saved. */ -void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs, +void radeon_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_saved_cs *saved, bool get_buffer_list) { uint32_t *buf; diff --git a/src/gallium/drivers/r600/r600_pipe_common.h b/src/gallium/drivers/r600/r600_pipe_common.h index ee8eb54920e..c4e60e9db89 100644 --- a/src/gallium/drivers/r600/r600_pipe_common.h +++ b/src/gallium/drivers/r600/r600_pipe_common.h @@ -488,7 +488,7 @@ struct r600_viewports { }; struct r600_ring { - struct radeon_winsys_cs *cs; + struct radeon_cmdbuf *cs; void (*flush)(void *ctx, unsigned flags, struct pipe_fence_handle **fence); }; @@ -708,7 +708,7 @@ struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen, const char *r600_get_llvm_processor_name(enum radeon_family family); void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw, struct r600_resource *dst, struct r600_resource *src); -void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs, +void radeon_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_saved_cs *saved, bool get_buffer_list); void radeon_clear_saved_cs(struct radeon_saved_cs *saved); bool r600_check_device_reset(struct r600_common_context *rctx); @@ -799,7 +799,7 @@ extern const unsigned eg_max_dist_4x; void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count, unsigned sample_index, float *out_value); void cayman_init_msaa(struct pipe_context *ctx); -void cayman_emit_msaa_state(struct radeon_winsys_cs *cs, int nr_samples, +void cayman_emit_msaa_state(struct radeon_cmdbuf *cs, int nr_samples, int ps_iter_samples, int overrast_samples); diff --git a/src/gallium/drivers/r600/r600_query.c b/src/gallium/drivers/r600/r600_query.c index 729c6f2aaa7..7058216c0cb 100644 --- a/src/gallium/drivers/r600/r600_query.c +++ b/src/gallium/drivers/r600/r600_query.c @@ -714,7 +714,7 @@ static unsigned event_type_for_stream(unsigned stream) } } -static void emit_sample_streamout(struct radeon_winsys_cs *cs, uint64_t va, +static void emit_sample_streamout(struct radeon_cmdbuf *cs, uint64_t va, unsigned stream) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); @@ -728,7 +728,7 @@ static void r600_query_hw_do_emit_start(struct r600_common_context *ctx, struct r600_resource *buffer, uint64_t va) { - struct radeon_winsys_cs *cs = ctx->gfx.cs; + struct radeon_cmdbuf *cs = ctx->gfx.cs; switch (query->b.type) { case PIPE_QUERY_OCCLUSION_COUNTER: @@ -808,7 +808,7 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx, struct r600_resource *buffer, uint64_t va) { - struct radeon_winsys_cs *cs = ctx->gfx.cs; + struct radeon_cmdbuf *cs = ctx->gfx.cs; uint64_t fence_va = 0; switch (query->b.type) { @@ -900,7 +900,7 @@ static void emit_set_predicate(struct r600_common_context *ctx, struct r600_resource *buf, uint64_t va, uint32_t op) { - struct radeon_winsys_cs *cs = ctx->gfx.cs; + struct radeon_cmdbuf *cs = ctx->gfx.cs; radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0)); radeon_emit(cs, va); @@ -1833,7 +1833,7 @@ void r600_query_fix_enabled_rb_mask(struct r600_common_screen *rscreen) { struct r600_common_context *ctx = (struct r600_common_context*)rscreen->aux_context; - struct radeon_winsys_cs *cs = ctx->gfx.cs; + struct radeon_cmdbuf *cs = ctx->gfx.cs; struct r600_resource *buffer; uint32_t *results; unsigned i, mask = 0; diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index a37a7018371..2c3a5ab4422 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -245,7 +245,7 @@ boolean r600_is_format_supported(struct pipe_screen *screen, static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a; float offset_units = state->offset_units; float offset_scale = state->offset_scale; @@ -791,7 +791,7 @@ r600_create_sampler_view(struct pipe_context *ctx, static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct pipe_clip_state *state = &rctx->clip_state.state; radeon_set_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4); @@ -1283,7 +1283,7 @@ static void r600_get_sample_position(struct pipe_context *ctx, static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; unsigned max_dist = 0; if (rctx->b.family == CHIP_R600) { @@ -1350,7 +1350,7 @@ static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples) static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct pipe_framebuffer_state *state = &rctx->framebuffer.state; unsigned nr_cbufs = state->nr_cbufs; struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0]; @@ -1516,7 +1516,7 @@ static void r600_set_min_samples(struct pipe_context *ctx, unsigned min_samples) static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom; if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) { @@ -1546,7 +1546,7 @@ static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_db_state *a = (struct r600_db_state*)atom; if (a->rsurf && a->rsurf->db_htile_surface) { @@ -1567,7 +1567,7 @@ static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom; unsigned db_render_control = 0; unsigned db_render_override = @@ -1652,7 +1652,7 @@ static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_config_state *a = (struct r600_config_state*)atom; radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1); @@ -1661,7 +1661,7 @@ static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom * static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask; while (dirty_mask) { @@ -1701,7 +1701,7 @@ static void r600_emit_constant_buffers(struct r600_context *rctx, unsigned reg_alu_constbuf_size, unsigned reg_alu_const_cache) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; uint32_t dirty_mask = state->dirty_mask; while (dirty_mask) { @@ -1775,7 +1775,7 @@ static void r600_emit_sampler_views(struct r600_context *rctx, struct r600_samplerview_state *state, unsigned resource_id_base) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; uint32_t dirty_mask = state->dirty_mask; while (dirty_mask) { @@ -1822,7 +1822,7 @@ static void r600_emit_sampler_states(struct r600_context *rctx, unsigned resource_id_base, unsigned border_color_reg) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; uint32_t dirty_mask = texinfo->states.dirty_mask; while (dirty_mask) { @@ -1883,7 +1883,7 @@ static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_a static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; unsigned tmp; tmp = S_009508_DISABLE_CUBE_ANISO(1) | @@ -1907,7 +1907,7 @@ static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_cso_state *state = (struct r600_cso_state*)a; struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso; @@ -1923,7 +1923,7 @@ static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a; uint32_t v2 = 0, primid = 0; @@ -1958,7 +1958,7 @@ static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a; struct r600_resource *rbuffer; @@ -2855,7 +2855,7 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx, unsigned pitch, unsigned bpp) { - struct radeon_winsys_cs *cs = rctx->b.dma.cs; + struct radeon_cmdbuf *cs = rctx->b.dma.cs; struct r600_texture *rsrc = (struct r600_texture*)src; struct r600_texture *rdst = (struct r600_texture*)dst; unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size; diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c index 9994f476cc2..1e775e565b5 100644 --- a/src/gallium/drivers/r600/r600_state_common.c +++ b/src/gallium/drivers/r600/r600_state_common.c @@ -77,7 +77,7 @@ void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom) void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom; unsigned alpha_ref = a->sx_alpha_ref; @@ -241,7 +241,7 @@ static void r600_set_blend_color(struct pipe_context *ctx, void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct pipe_blend_color *state = &rctx->blend_color.state; radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4); @@ -253,7 +253,7 @@ void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom) void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_vgt_state *a = (struct r600_vgt_state *)atom; radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en); @@ -287,7 +287,7 @@ static void r600_set_stencil_ref(struct pipe_context *ctx, void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom; radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2); @@ -1625,7 +1625,7 @@ void r600_setup_scratch_area_for_shader(struct r600_context *rctx, if (scratch->dirty || unlikely(shader->scratch_space_needed != scratch->item_size || size > scratch->size)) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; scratch->dirty = false; @@ -1969,7 +1969,7 @@ static bool r600_update_derived_state(struct r600_context *rctx) void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_clip_misc_state *state = &rctx->clip_misc_state; radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL, @@ -1989,7 +1989,7 @@ void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom /* rast_prim is the primitive type after GS. */ static inline void r600_emit_rasterizer_prim_state(struct r600_context *rctx) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; enum pipe_prim_type rast_prim = rctx->current_rast_prim; /* Skip this if not rendering lines. */ @@ -2016,7 +2016,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info { struct r600_context *rctx = (struct r600_context *)ctx; struct pipe_resource *indexbuf = info->has_user_indices ? NULL : info->index.resource; - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; bool render_cond_bit = rctx->b.render_cond && !rctx->b.render_cond_force_off; bool has_user_indices = info->has_user_indices; uint64_t mask; @@ -2531,7 +2531,7 @@ bool sampler_state_needs_border_color(const struct pipe_sampler_state *state) void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a) { - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct radeon_cmdbuf *cs = rctx->b.gfx.cs; struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader; if (!shader) diff --git a/src/gallium/drivers/r600/r600_streamout.c b/src/gallium/drivers/r600/r600_streamout.c index 78334066c39..de3e767acc0 100644 --- a/src/gallium/drivers/r600/r600_streamout.c +++ b/src/gallium/drivers/r600/r600_streamout.c @@ -154,7 +154,7 @@ void r600_set_streamout_targets(struct pipe_context *ctx, static void r600_flush_vgt_streamout(struct r600_common_context *rctx) { - struct radeon_winsys_cs *cs = rctx->gfx.cs; + struct radeon_cmdbuf *cs = rctx->gfx.cs; unsigned reg_strmout_cntl; /* The register is at different places on different ASICs. */ @@ -180,7 +180,7 @@ static void r600_flush_vgt_streamout(struct r600_common_context *rctx) static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r600_atom *atom) { - struct radeon_winsys_cs *cs = rctx->gfx.cs; + struct radeon_cmdbuf *cs = rctx->gfx.cs; struct r600_so_target **t = rctx->streamout.targets; uint16_t *stride_in_dw = rctx->streamout.stride_in_dw; unsigned i, update_flags = 0; @@ -253,7 +253,7 @@ static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r void r600_emit_streamout_end(struct r600_common_context *rctx) { - struct radeon_winsys_cs *cs = rctx->gfx.cs; + struct radeon_cmdbuf *cs = rctx->gfx.cs; struct r600_so_target **t = rctx->streamout.targets; unsigned i; uint64_t va; diff --git a/src/gallium/drivers/r600/r600_viewport.c b/src/gallium/drivers/r600/r600_viewport.c index 0797f932fb8..7a5bf8f39aa 100644 --- a/src/gallium/drivers/r600/r600_viewport.c +++ b/src/gallium/drivers/r600/r600_viewport.c @@ -154,7 +154,7 @@ void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx, } static void r600_emit_one_scissor(struct r600_common_context *rctx, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, struct r600_signed_scissor *vp_scissor, struct pipe_scissor_state *scissor) { @@ -185,7 +185,7 @@ static void r600_emit_one_scissor(struct r600_common_context *rctx, static void r600_emit_guardband(struct r600_common_context *rctx, struct r600_signed_scissor *vp_as_scissor) { - struct radeon_winsys_cs *cs = rctx->gfx.cs; + struct radeon_cmdbuf *cs = rctx->gfx.cs; struct pipe_viewport_state vp; float left, top, right, bottom, max_range, guardband_x, guardband_y; @@ -235,7 +235,7 @@ static void r600_emit_guardband(struct r600_common_context *rctx, static void r600_emit_scissors(struct r600_common_context *rctx, struct r600_atom *atom) { - struct radeon_winsys_cs *cs = rctx->gfx.cs; + struct radeon_cmdbuf *cs = rctx->gfx.cs; struct pipe_scissor_state *states = rctx->scissors.states; unsigned mask = rctx->scissors.dirty_mask; bool scissor_enabled = rctx->scissor_enabled; @@ -306,7 +306,7 @@ static void r600_set_viewport_states(struct pipe_context *ctx, static void r600_emit_one_viewport(struct r600_common_context *rctx, struct pipe_viewport_state *state) { - struct radeon_winsys_cs *cs = rctx->gfx.cs; + struct radeon_cmdbuf *cs = rctx->gfx.cs; radeon_emit(cs, fui(state->scale[0])); radeon_emit(cs, fui(state->translate[0])); @@ -318,7 +318,7 @@ static void r600_emit_one_viewport(struct r600_common_context *rctx, static void r600_emit_viewports(struct r600_common_context *rctx) { - struct radeon_winsys_cs *cs = rctx->gfx.cs; + struct radeon_cmdbuf *cs = rctx->gfx.cs; struct pipe_viewport_state *states = rctx->viewports.states; unsigned mask = rctx->viewports.dirty_mask; @@ -348,7 +348,7 @@ static void r600_emit_viewports(struct r600_common_context *rctx) static void r600_emit_depth_ranges(struct r600_common_context *rctx) { - struct radeon_winsys_cs *cs = rctx->gfx.cs; + struct radeon_cmdbuf *cs = rctx->gfx.cs; struct pipe_viewport_state *states = rctx->viewports.states; unsigned mask = rctx->viewports.depth_range_dirty_mask; float zmin, zmax; diff --git a/src/gallium/drivers/r600/radeon_uvd.c b/src/gallium/drivers/r600/radeon_uvd.c index 17ff3d5d72a..1c4094e809f 100644 --- a/src/gallium/drivers/r600/radeon_uvd.c +++ b/src/gallium/drivers/r600/radeon_uvd.c @@ -73,7 +73,7 @@ struct ruvd_decoder { struct pipe_screen *screen; struct radeon_winsys* ws; - struct radeon_winsys_cs* cs; + struct radeon_cmdbuf* cs; unsigned cur_buffer; diff --git a/src/gallium/drivers/r600/radeon_vce.h b/src/gallium/drivers/r600/radeon_vce.h index f79e65c9ac2..71f028721b4 100644 --- a/src/gallium/drivers/r600/radeon_vce.h +++ b/src/gallium/drivers/r600/radeon_vce.h @@ -387,7 +387,7 @@ struct rvce_encoder { struct pipe_screen *screen; struct radeon_winsys* ws; - struct radeon_winsys_cs* cs; + struct radeon_cmdbuf* cs; rvce_get_buffer get_buffer; diff --git a/src/gallium/drivers/r600/radeon_video.c b/src/gallium/drivers/r600/radeon_video.c index c7acc3d6e22..02fcf77d4ff 100644 --- a/src/gallium/drivers/r600/radeon_video.c +++ b/src/gallium/drivers/r600/radeon_video.c @@ -85,7 +85,7 @@ void rvid_destroy_buffer(struct rvid_buffer *buffer) } /* reallocate a buffer, preserving its content */ -bool rvid_resize_buffer(struct pipe_screen *screen, struct radeon_winsys_cs *cs, +bool rvid_resize_buffer(struct pipe_screen *screen, struct radeon_cmdbuf *cs, struct rvid_buffer *new_buf, unsigned new_size) { struct r600_common_screen *rscreen = (struct r600_common_screen *)screen; diff --git a/src/gallium/drivers/r600/radeon_video.h b/src/gallium/drivers/r600/radeon_video.h index 3347c4ebced..8befc2f85df 100644 --- a/src/gallium/drivers/r600/radeon_video.h +++ b/src/gallium/drivers/r600/radeon_video.h @@ -58,7 +58,7 @@ bool rvid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer, void rvid_destroy_buffer(struct rvid_buffer *buffer); /* reallocate a buffer, preserving its content */ -bool rvid_resize_buffer(struct pipe_screen *screen, struct radeon_winsys_cs *cs, +bool rvid_resize_buffer(struct pipe_screen *screen, struct radeon_cmdbuf *cs, struct rvid_buffer *new_buf, unsigned new_size); /* clear the buffer with zeros */ diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c index 92336ed377d..dbf3c95175c 100644 --- a/src/gallium/drivers/radeon/radeon_uvd.c +++ b/src/gallium/drivers/radeon/radeon_uvd.c @@ -67,7 +67,7 @@ struct ruvd_decoder { struct pipe_screen *screen; struct radeon_winsys* ws; - struct radeon_winsys_cs* cs; + struct radeon_cmdbuf* cs; unsigned cur_buffer; diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.h b/src/gallium/drivers/radeon/radeon_uvd_enc.h index 20c340ddecb..63176d264c2 100644 --- a/src/gallium/drivers/radeon/radeon_uvd_enc.h +++ b/src/gallium/drivers/radeon/radeon_uvd_enc.h @@ -433,7 +433,7 @@ struct radeon_uvd_encoder struct pipe_screen *screen; struct radeon_winsys *ws; - struct radeon_winsys_cs *cs; + struct radeon_cmdbuf *cs; radeon_uvd_enc_get_buffer get_buffer; diff --git a/src/gallium/drivers/radeon/radeon_vce.h b/src/gallium/drivers/radeon/radeon_vce.h index 7f30877c727..cf625e6fed7 100644 --- a/src/gallium/drivers/radeon/radeon_vce.h +++ b/src/gallium/drivers/radeon/radeon_vce.h @@ -381,7 +381,7 @@ struct rvce_encoder { struct pipe_screen *screen; struct radeon_winsys* ws; - struct radeon_winsys_cs* cs; + struct radeon_cmdbuf* cs; rvce_get_buffer get_buffer; diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c index 8c56be92ce6..aac2c8fa83c 100644 --- a/src/gallium/drivers/radeon/radeon_vcn_dec.c +++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c @@ -66,7 +66,7 @@ struct radeon_decoder { struct pipe_screen *screen; struct radeon_winsys *ws; - struct radeon_winsys_cs *cs; + struct radeon_cmdbuf *cs; void *msg; uint32_t *fb; diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.h b/src/gallium/drivers/radeon/radeon_vcn_enc.h index 9f0c909c676..04685c69af1 100644 --- a/src/gallium/drivers/radeon/radeon_vcn_enc.h +++ b/src/gallium/drivers/radeon/radeon_vcn_enc.h @@ -455,7 +455,7 @@ struct radeon_encoder { struct pipe_screen *screen; struct radeon_winsys* ws; - struct radeon_winsys_cs* cs; + struct radeon_cmdbuf* cs; radeon_enc_get_buffer get_buffer; diff --git a/src/gallium/drivers/radeon/radeon_video.c b/src/gallium/drivers/radeon/radeon_video.c index f59b44736aa..749f30c2306 100644 --- a/src/gallium/drivers/radeon/radeon_video.c +++ b/src/gallium/drivers/radeon/radeon_video.c @@ -76,7 +76,7 @@ void si_vid_destroy_buffer(struct rvid_buffer *buffer) } /* reallocate a buffer, preserving its content */ -bool si_vid_resize_buffer(struct pipe_screen *screen, struct radeon_winsys_cs *cs, +bool si_vid_resize_buffer(struct pipe_screen *screen, struct radeon_cmdbuf *cs, struct rvid_buffer *new_buf, unsigned new_size) { struct si_screen *sscreen = (struct si_screen *)screen; diff --git a/src/gallium/drivers/radeon/radeon_video.h b/src/gallium/drivers/radeon/radeon_video.h index eee550c44b1..71904b313f4 100644 --- a/src/gallium/drivers/radeon/radeon_video.h +++ b/src/gallium/drivers/radeon/radeon_video.h @@ -54,7 +54,7 @@ bool si_vid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer void si_vid_destroy_buffer(struct rvid_buffer *buffer); /* reallocate a buffer, preserving its content */ -bool si_vid_resize_buffer(struct pipe_screen *screen, struct radeon_winsys_cs *cs, +bool si_vid_resize_buffer(struct pipe_screen *screen, struct radeon_cmdbuf *cs, struct rvid_buffer *new_buf, unsigned new_size); /* clear the buffer with zeros */ diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h index abf70ce762b..22ec47b9dc8 100644 --- a/src/gallium/drivers/radeon/radeon_winsys.h +++ b/src/gallium/drivers/radeon/radeon_winsys.h @@ -171,15 +171,15 @@ enum radeon_bo_priority { struct winsys_handle; struct radeon_winsys_ctx; -struct radeon_winsys_cs_chunk { +struct radeon_cmdbuf_chunk { unsigned cdw; /* Number of used dwords. */ unsigned max_dw; /* Maximum number of dwords. */ uint32_t *buf; /* The base pointer of the chunk. */ }; -struct radeon_winsys_cs { - struct radeon_winsys_cs_chunk current; - struct radeon_winsys_cs_chunk *prev; +struct radeon_cmdbuf { + struct radeon_cmdbuf_chunk current; + struct radeon_cmdbuf_chunk *prev; unsigned num_prev; /* Number of previous chunks. */ unsigned max_prev; /* Space in array pointed to by prev. */ unsigned prev_dw; /* Total number of dwords in previous chunks. */ @@ -297,7 +297,7 @@ struct radeon_winsys { * \return The pointer at the beginning of the buffer. */ void *(*buffer_map)(struct pb_buffer *buf, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, enum pipe_transfer_usage usage); /** @@ -460,7 +460,7 @@ struct radeon_winsys { * \param flush Flush callback function associated with the command stream. * \param user User pointer that will be passed to the flush callback. */ - struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx, + struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys_ctx *ctx, enum ring_type ring_type, void (*flush)(void *ctx, unsigned flags, struct pipe_fence_handle **fence), @@ -471,7 +471,7 @@ struct radeon_winsys { * * \param cs A command stream to destroy. */ - void (*cs_destroy)(struct radeon_winsys_cs *cs); + void (*cs_destroy)(struct radeon_cmdbuf *cs); /** * Add a buffer. Each buffer used by a CS must be added using this function. @@ -484,7 +484,7 @@ struct radeon_winsys { * placed in the requested domain. 15 is the maximum. * \return Buffer index. */ - unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs, + unsigned (*cs_add_buffer)(struct radeon_cmdbuf *cs, struct pb_buffer *buf, enum radeon_bo_usage usage, enum radeon_bo_domain domain, @@ -500,7 +500,7 @@ struct radeon_winsys { * \param buf Buffer * \return The buffer index, or -1 if the buffer has not been added. */ - int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs, + int (*cs_lookup_buffer)(struct radeon_cmdbuf *cs, struct pb_buffer *buf); /** @@ -511,7 +511,7 @@ struct radeon_winsys { * * \param cs A command stream to validate. */ - bool (*cs_validate)(struct radeon_winsys_cs *cs); + bool (*cs_validate)(struct radeon_cmdbuf *cs); /** * Check whether the given number of dwords is available in the IB. @@ -520,7 +520,7 @@ struct radeon_winsys { * \param cs A command stream. * \param dw Number of CS dwords requested by the caller. */ - bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw); + bool (*cs_check_space)(struct radeon_cmdbuf *cs, unsigned dw); /** * Return the buffer list. @@ -532,7 +532,7 @@ struct radeon_winsys { * \param list Returned buffer list. Set to NULL to query the count only. * \return The buffer count. */ - unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs, + unsigned (*cs_get_buffer_list)(struct radeon_cmdbuf *cs, struct radeon_bo_list_item *list); /** @@ -545,7 +545,7 @@ struct radeon_winsys { * \return Negative POSIX error code or 0 for success. * Asynchronous submissions never return an error. */ - int (*cs_flush)(struct radeon_winsys_cs *cs, + int (*cs_flush)(struct radeon_cmdbuf *cs, unsigned flags, struct pipe_fence_handle **fence); @@ -556,7 +556,7 @@ struct radeon_winsys { * The fence must not be used for anything except \ref cs_add_fence_dependency * before the flush. */ - struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_winsys_cs *cs); + struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_cmdbuf *cs); /** * Return true if a buffer is referenced by a command stream. @@ -564,7 +564,7 @@ struct radeon_winsys { * \param cs A command stream. * \param buf A winsys buffer. */ - bool (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs, + bool (*cs_is_buffer_referenced)(struct radeon_cmdbuf *cs, struct pb_buffer *buf, enum radeon_bo_usage usage); @@ -575,7 +575,7 @@ struct radeon_winsys { * \param fid Feature ID, one of RADEON_FID_* * \param enable Whether to enable or disable the feature. */ - bool (*cs_request_feature)(struct radeon_winsys_cs *cs, + bool (*cs_request_feature)(struct radeon_cmdbuf *cs, enum radeon_feature_id fid, bool enable); /** @@ -583,19 +583,19 @@ struct radeon_winsys { * * \param cs A command stream. */ - void (*cs_sync_flush)(struct radeon_winsys_cs *cs); + void (*cs_sync_flush)(struct radeon_cmdbuf *cs); /** * Add a fence dependency to the CS, so that the CS will wait for * the fence before execution. */ - void (*cs_add_fence_dependency)(struct radeon_winsys_cs *cs, + void (*cs_add_fence_dependency)(struct radeon_cmdbuf *cs, struct pipe_fence_handle *fence); /** * Signal a syncobj when the CS finishes execution. */ - void (*cs_add_syncobj_signal)(struct radeon_winsys_cs *cs, + void (*cs_add_syncobj_signal)(struct radeon_cmdbuf *cs, struct pipe_fence_handle *fence); /** @@ -663,17 +663,17 @@ struct radeon_winsys { const char* (*get_chip_name)(struct radeon_winsys *ws); }; -static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw) +static inline bool radeon_emitted(struct radeon_cmdbuf *cs, unsigned num_dw) { return cs && (cs->prev_dw + cs->current.cdw > num_dw); } -static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value) +static inline void radeon_emit(struct radeon_cmdbuf *cs, uint32_t value) { cs->current.buf[cs->current.cdw++] = value; } -static inline void radeon_emit_array(struct radeon_winsys_cs *cs, +static inline void radeon_emit_array(struct radeon_cmdbuf *cs, const uint32_t *values, unsigned count) { memcpy(cs->current.buf + cs->current.cdw, values, count * 4); diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c b/src/gallium/drivers/radeonsi/cik_sdma.c index 7a4b479b7eb..1eaa49fea3e 100644 --- a/src/gallium/drivers/radeonsi/cik_sdma.c +++ b/src/gallium/drivers/radeonsi/cik_sdma.c @@ -33,7 +33,7 @@ static void cik_sdma_copy_buffer(struct si_context *ctx, uint64_t src_offset, uint64_t size) { - struct radeon_winsys_cs *cs = ctx->dma_cs; + struct radeon_cmdbuf *cs = ctx->dma_cs; unsigned i, ncopy, csize; struct r600_resource *rdst = r600_resource(dst); struct r600_resource *rsrc = r600_resource(src); @@ -73,7 +73,7 @@ static void cik_sdma_clear_buffer(struct si_context *sctx, uint64_t size, unsigned clear_value) { - struct radeon_winsys_cs *cs = sctx->dma_cs; + struct radeon_cmdbuf *cs = sctx->dma_cs; unsigned i, ncopy, csize; struct r600_resource *rdst = r600_resource(dst); @@ -230,7 +230,7 @@ static bool cik_sdma_copy_texture(struct si_context *sctx, sctx->family != CHIP_KAVERI) || (srcx + copy_width != (1 << 14) && srcy + copy_height != (1 << 14)))) { - struct radeon_winsys_cs *cs = sctx->dma_cs; + struct radeon_cmdbuf *cs = sctx->dma_cs; si_need_dma_space(sctx, 13, &rdst->buffer, &rsrc->buffer); @@ -392,7 +392,7 @@ static bool cik_sdma_copy_texture(struct si_context *sctx, copy_width_aligned <= (1 << 14) && copy_height <= (1 << 14) && copy_depth <= (1 << 11)) { - struct radeon_winsys_cs *cs = sctx->dma_cs; + struct radeon_cmdbuf *cs = sctx->dma_cs; uint32_t direction = linear == rdst ? 1u << 31 : 0; si_need_dma_space(sctx, 14, &rdst->buffer, &rsrc->buffer); @@ -487,7 +487,7 @@ static bool cik_sdma_copy_texture(struct si_context *sctx, (srcx + copy_width_aligned != (1 << 14) && srcy + copy_height_aligned != (1 << 14) && dstx + copy_width != (1 << 14)))) { - struct radeon_winsys_cs *cs = sctx->dma_cs; + struct radeon_cmdbuf *cs = sctx->dma_cs; si_need_dma_space(sctx, 15, &rdst->buffer, &rsrc->buffer); diff --git a/src/gallium/drivers/radeonsi/si_build_pm4.h b/src/gallium/drivers/radeonsi/si_build_pm4.h index aa4e5a303f6..0c92b1a35c0 100644 --- a/src/gallium/drivers/radeonsi/si_build_pm4.h +++ b/src/gallium/drivers/radeonsi/si_build_pm4.h @@ -32,7 +32,7 @@ #include "si_pipe.h" #include "sid.h" -static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) +static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) { assert(reg < SI_CONTEXT_REG_OFFSET); assert(cs->current.cdw + 2 + num <= cs->current.max_dw); @@ -40,13 +40,13 @@ static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsign radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2); } -static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) +static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) { radeon_set_config_reg_seq(cs, reg, 1); radeon_emit(cs, value); } -static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) +static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) { assert(reg >= SI_CONTEXT_REG_OFFSET); assert(cs->current.cdw + 2 + num <= cs->current.max_dw); @@ -54,13 +54,13 @@ static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsig radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); } -static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) +static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) { radeon_set_context_reg_seq(cs, reg, 1); radeon_emit(cs, value); } -static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs, +static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, unsigned value) { @@ -71,7 +71,7 @@ static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs, radeon_emit(cs, value); } -static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) +static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) { assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END); assert(cs->current.cdw + 2 + num <= cs->current.max_dw); @@ -79,13 +79,13 @@ static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned r radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2); } -static inline void radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) +static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) { radeon_set_sh_reg_seq(cs, reg, 1); radeon_emit(cs, value); } -static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) +static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) { assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); assert(cs->current.cdw + 2 + num <= cs->current.max_dw); @@ -93,13 +93,13 @@ static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsig radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); } -static inline void radeon_set_uconfig_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) +static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) { radeon_set_uconfig_reg_seq(cs, reg, 1); radeon_emit(cs, value); } -static inline void radeon_set_uconfig_reg_idx(struct radeon_winsys_cs *cs, +static inline void radeon_set_uconfig_reg_idx(struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, unsigned value) { @@ -114,7 +114,7 @@ static inline void radeon_set_uconfig_reg_idx(struct radeon_winsys_cs *cs, static inline void radeon_opt_set_context_reg(struct si_context *sctx, unsigned offset, enum si_tracked_reg reg, unsigned value) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; if (!(sctx->tracked_regs.reg_saved & (1 << reg)) || sctx->tracked_regs.reg_value[reg] != value ) { @@ -136,7 +136,7 @@ static inline void radeon_opt_set_context_reg2(struct si_context *sctx, unsigned enum si_tracked_reg reg, unsigned value1, unsigned value2) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; if (!(sctx->tracked_regs.reg_saved & (1 << reg)) || !(sctx->tracked_regs.reg_saved & (1 << (reg + 1))) || @@ -160,7 +160,7 @@ static inline void radeon_opt_set_context_reg3(struct si_context *sctx, unsigned enum si_tracked_reg reg, unsigned value1, unsigned value2, unsigned value3) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; if (!(sctx->tracked_regs.reg_saved & (1 << reg)) || !(sctx->tracked_regs.reg_saved & (1 << (reg + 1))) || diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index e20bae0afc4..cb320323db3 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -292,7 +292,7 @@ static void si_set_global_binding( static void si_initialize_compute(struct si_context *sctx) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; uint64_t bc_va; radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2); @@ -385,7 +385,7 @@ static bool si_switch_compute_shader(struct si_context *sctx, const amd_kernel_code_t *code_object, unsigned offset) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; struct si_shader_config inline_config = {0}; struct si_shader_config *config; uint64_t shader_va; @@ -489,7 +489,7 @@ static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx, const amd_kernel_code_t *code_object, unsigned user_sgpr) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address; unsigned max_private_element_size = AMD_HSA_BITS_GET( @@ -534,7 +534,7 @@ static void si_setup_user_sgprs_co_v2(struct si_context *sctx, uint64_t kernel_args_va) { struct si_compute *program = sctx->cs_shader_state.program; - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; static const enum amd_code_property_mask_t workgroup_count_masks [] = { AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X, @@ -623,7 +623,7 @@ static bool si_upload_compute_input(struct si_context *sctx, const amd_kernel_code_t *code_object, const struct pipe_grid_info *info) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; struct si_compute *program = sctx->cs_shader_state.program; struct r600_resource *input_buffer = NULL; unsigned kernel_args_size; @@ -687,7 +687,7 @@ static void si_setup_tgsi_grid(struct si_context *sctx, const struct pipe_grid_info *info) { struct si_compute *program = sctx->cs_shader_state.program; - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 + 4 * SI_NUM_RESOURCE_SGPRS; unsigned block_size_reg = grid_size_reg + @@ -734,7 +734,7 @@ static void si_emit_dispatch_packets(struct si_context *sctx, const struct pipe_grid_info *info) { struct si_screen *sscreen = sctx->screen; - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off; unsigned waves_per_threadgroup = DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64); diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c index b3621f794f5..db26dec8c49 100644 --- a/src/gallium/drivers/radeonsi/si_cp_dma.c +++ b/src/gallium/drivers/radeonsi/si_cp_dma.c @@ -62,7 +62,7 @@ static void si_emit_cp_dma(struct si_context *sctx, uint64_t dst_va, uint64_t src_va, unsigned size, unsigned flags, enum si_coherency coher) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; uint32_t header = 0, command = 0; assert(size <= cp_dma_max_byte_count(sctx)); diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c index 36cbb8866ed..917ec54579a 100644 --- a/src/gallium/drivers/radeonsi/si_debug.c +++ b/src/gallium/drivers/radeonsi/si_debug.c @@ -43,7 +43,7 @@ DEBUG_GET_ONCE_OPTION(replace_shaders, "RADEON_REPLACE_SHADERS", NULL) * Store a linearized copy of all chunks of \p cs together with the buffer * list in \p saved. */ -void si_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs, +void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_saved_cs *saved, bool get_buffer_list) { uint32_t *buf; @@ -346,7 +346,7 @@ static void si_log_chunk_type_cs_destroy(void *data) free(chunk); } -static void si_parse_current_ib(FILE *f, struct radeon_winsys_cs *cs, +static void si_parse_current_ib(FILE *f, struct radeon_cmdbuf *cs, unsigned begin, unsigned end, int *last_trace_id, unsigned trace_id_count, const char *name, enum chip_class chip_class) @@ -359,7 +359,7 @@ static void si_parse_current_ib(FILE *f, struct radeon_winsys_cs *cs, name, begin); for (unsigned prev_idx = 0; prev_idx < cs->num_prev; ++prev_idx) { - struct radeon_winsys_cs_chunk *chunk = &cs->prev[prev_idx]; + struct radeon_cmdbuf_chunk *chunk = &cs->prev[prev_idx]; if (begin < chunk->cdw) { ac_parse_ib_chunk(f, chunk->buf + begin, diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 57a312463c9..dac1f45bcb1 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -1809,7 +1809,7 @@ static void si_upload_bindless_descriptor(struct si_context *sctx, unsigned num_dwords) { struct si_descriptors *desc = &sctx->bindless_descriptors; - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; unsigned desc_slot_offset = desc_slot * 16; uint32_t *data; uint64_t va; @@ -2055,7 +2055,7 @@ void si_shader_change_notify(struct si_context *sctx) } } -static void si_emit_shader_pointer_head(struct radeon_winsys_cs *cs, +static void si_emit_shader_pointer_head(struct radeon_cmdbuf *cs, unsigned sh_offset, unsigned pointer_count) { @@ -2064,7 +2064,7 @@ static void si_emit_shader_pointer_head(struct radeon_winsys_cs *cs, } static void si_emit_shader_pointer_body(struct si_screen *sscreen, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, uint64_t va) { radeon_emit(cs, va); @@ -2079,7 +2079,7 @@ static void si_emit_shader_pointer(struct si_context *sctx, struct si_descriptors *desc, unsigned sh_base) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; unsigned sh_offset = sh_base + desc->shader_userdata_offset; si_emit_shader_pointer_head(cs, sh_offset, 1); @@ -2093,7 +2093,7 @@ static void si_emit_consecutive_shader_pointers(struct si_context *sctx, if (!sh_base) return; - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; unsigned mask = sctx->shader_pointers_dirty & pointer_mask; while (mask) { @@ -2117,7 +2117,7 @@ static void si_emit_disjoint_shader_pointers(struct si_context *sctx, if (!sh_base) return; - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; unsigned mask = sctx->shader_pointers_dirty & pointer_mask; while (mask) { @@ -2184,7 +2184,7 @@ void si_emit_graphics_shader_pointers(struct si_context *sctx) ~u_bit_consecutive(SI_DESCS_RW_BUFFERS, SI_DESCS_FIRST_COMPUTE); if (sctx->vertex_buffer_pointer_dirty) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; /* Find the location of the VB descriptor pointer. */ /* TODO: In the future, the pointer will be packed in unused diff --git a/src/gallium/drivers/radeonsi/si_dma.c b/src/gallium/drivers/radeonsi/si_dma.c index 7bdee525be1..5d78a50cfe2 100644 --- a/src/gallium/drivers/radeonsi/si_dma.c +++ b/src/gallium/drivers/radeonsi/si_dma.c @@ -35,7 +35,7 @@ static void si_dma_copy_buffer(struct si_context *ctx, uint64_t src_offset, uint64_t size) { - struct radeon_winsys_cs *cs = ctx->dma_cs; + struct radeon_cmdbuf *cs = ctx->dma_cs; unsigned i, ncopy, count, max_size, sub_cmd, shift; struct r600_resource *rdst = r600_resource(dst); struct r600_resource *rsrc = r600_resource(src); @@ -83,7 +83,7 @@ static void si_dma_clear_buffer(struct si_context *sctx, uint64_t size, unsigned clear_value) { - struct radeon_winsys_cs *cs = sctx->dma_cs; + struct radeon_cmdbuf *cs = sctx->dma_cs; unsigned i, ncopy, csize; struct r600_resource *rdst = r600_resource(dst); @@ -131,7 +131,7 @@ static void si_dma_copy_tile(struct si_context *ctx, unsigned pitch, unsigned bpp) { - struct radeon_winsys_cs *cs = ctx->dma_cs; + struct radeon_cmdbuf *cs = ctx->dma_cs; struct r600_texture *rsrc = (struct r600_texture*)src; struct r600_texture *rdst = (struct r600_texture*)dst; unsigned dst_mode = rdst->surface.u.legacy.level[dst_level].mode; diff --git a/src/gallium/drivers/radeonsi/si_dma_cs.c b/src/gallium/drivers/radeonsi/si_dma_cs.c index 1eefaeb6ad5..a0dec39b6bb 100644 --- a/src/gallium/drivers/radeonsi/si_dma_cs.c +++ b/src/gallium/drivers/radeonsi/si_dma_cs.c @@ -26,7 +26,7 @@ static void si_dma_emit_wait_idle(struct si_context *sctx) { - struct radeon_winsys_cs *cs = sctx->dma_cs; + struct radeon_cmdbuf *cs = sctx->dma_cs; /* NOP waits for idle on Evergreen and later. */ if (sctx->chip_class >= CIK) @@ -109,7 +109,7 @@ void si_need_dma_space(struct si_context *ctx, unsigned num_dw, void si_flush_dma_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_handle **fence) { - struct radeon_winsys_cs *cs = ctx->dma_cs; + struct radeon_cmdbuf *cs = ctx->dma_cs; struct radeon_saved_cs saved; bool check_vm = (ctx->screen->debug_flags & DBG(CHECK_VM)) != 0; diff --git a/src/gallium/drivers/radeonsi/si_fence.c b/src/gallium/drivers/radeonsi/si_fence.c index 19fcb96041f..186a785437d 100644 --- a/src/gallium/drivers/radeonsi/si_fence.c +++ b/src/gallium/drivers/radeonsi/si_fence.c @@ -70,7 +70,7 @@ void si_gfx_write_event_eop(struct si_context *ctx, struct r600_resource *buf, uint64_t va, uint32_t new_fence, unsigned query_type) { - struct radeon_winsys_cs *cs = ctx->gfx_cs; + struct radeon_cmdbuf *cs = ctx->gfx_cs; unsigned op = EVENT_TYPE(event) | EVENT_INDEX(5) | event_flags; @@ -163,7 +163,7 @@ unsigned si_gfx_write_fence_dwords(struct si_screen *screen) void si_gfx_wait_fence(struct si_context *ctx, uint64_t va, uint32_t ref, uint32_t mask) { - struct radeon_winsys_cs *cs = ctx->gfx_cs; + struct radeon_cmdbuf *cs = ctx->gfx_cs; radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1)); @@ -266,7 +266,7 @@ static void si_fine_fence_set(struct si_context *ctx, radeon_add_to_buffer_list(ctx, ctx->gfx_cs, fine->buf, RADEON_USAGE_WRITE, RADEON_PRIO_QUERY); if (flags & PIPE_FLUSH_TOP_OF_PIPE) { - struct radeon_winsys_cs *cs = ctx->gfx_cs; + struct radeon_cmdbuf *cs = ctx->gfx_cs; radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0)); radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) | S_370_WR_CONFIRM(1) | diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c index e01705d0775..09f0d3b8d4a 100644 --- a/src/gallium/drivers/radeonsi/si_gfx_cs.c +++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c @@ -30,7 +30,7 @@ /* initialize */ void si_need_gfx_cs_space(struct si_context *ctx) { - struct radeon_winsys_cs *cs = ctx->gfx_cs; + struct radeon_cmdbuf *cs = ctx->gfx_cs; /* There is no need to flush the DMA IB here, because * r600_need_dma_space always flushes the GFX IB if there is @@ -67,7 +67,7 @@ void si_need_gfx_cs_space(struct si_context *ctx) void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_handle **fence) { - struct radeon_winsys_cs *cs = ctx->gfx_cs; + struct radeon_cmdbuf *cs = ctx->gfx_cs; struct radeon_winsys *ws = ctx->ws; unsigned wait_flags = 0; diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c b/src/gallium/drivers/radeonsi/si_perfcounter.c index 346d4c50044..43bf887b774 100644 --- a/src/gallium/drivers/radeonsi/si_perfcounter.c +++ b/src/gallium/drivers/radeonsi/si_perfcounter.c @@ -425,7 +425,7 @@ static struct si_pc_block groups_gfx9[] = { static void si_pc_emit_instance(struct si_context *sctx, int se, int instance) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; unsigned value = S_030800_SH_BROADCAST_WRITES(1); if (se >= 0) { @@ -446,7 +446,7 @@ static void si_pc_emit_instance(struct si_context *sctx, static void si_pc_emit_shaders(struct si_context *sctx, unsigned shaders) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; radeon_set_uconfig_reg_seq(cs, R_036780_SQ_PERFCOUNTER_CTRL, 2); radeon_emit(cs, shaders & 0x7f); @@ -459,7 +459,7 @@ static void si_pc_emit_select(struct si_context *sctx, { struct si_pc_block *sigroup = (struct si_pc_block *)group->data; struct si_pc_block_base *regs = sigroup->b; - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; unsigned idx; unsigned layout_multi = regs->layout & SI_PC_MULTI_MASK; unsigned dw; @@ -552,7 +552,7 @@ static void si_pc_emit_select(struct si_context *sctx, static void si_pc_emit_start(struct si_context *sctx, struct r600_resource *buffer, uint64_t va) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; radeon_add_to_buffer_list(sctx, sctx->gfx_cs, buffer, RADEON_USAGE_WRITE, RADEON_PRIO_QUERY); @@ -578,7 +578,7 @@ static void si_pc_emit_start(struct si_context *sctx, static void si_pc_emit_stop(struct si_context *sctx, struct r600_resource *buffer, uint64_t va) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; si_gfx_write_event_eop(sctx, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DATA_SEL_VALUE_32BIT, @@ -601,7 +601,7 @@ static void si_pc_emit_read(struct si_context *sctx, { struct si_pc_block *sigroup = (struct si_pc_block *)group->data; struct si_pc_block_base *regs = sigroup->b; - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; unsigned idx; unsigned reg = regs->counter0_lo; unsigned reg_delta = 8; diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index cc871b1cc9f..bf316dedb30 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -536,7 +536,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, goto fail; /* Initialize the memory. */ - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0)); radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) | S_370_WR_CONFIRM(1) | diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 5ff762296fc..173d73e3c2c 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -744,8 +744,8 @@ struct si_context { struct radeon_winsys *ws; struct radeon_winsys_ctx *ctx; - struct radeon_winsys_cs *gfx_cs; - struct radeon_winsys_cs *dma_cs; + struct radeon_cmdbuf *gfx_cs; + struct radeon_cmdbuf *dma_cs; struct pipe_fence_handle *last_gfx_fence; struct pipe_fence_handle *last_sdma_fence; struct r600_resource *eop_bug_scratch; @@ -1132,7 +1132,7 @@ void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only); void si_init_cp_dma_functions(struct si_context *sctx); /* si_debug.c */ -void si_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs, +void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_saved_cs *saved, bool get_buffer_list); void si_clear_saved_cs(struct radeon_saved_cs *saved); void si_destroy_saved_cs(struct si_saved_cs *scs); @@ -1531,7 +1531,7 @@ static inline bool util_prim_is_points_or_lines(unsigned prim) */ static inline bool radeon_cs_memory_below_limit(struct si_screen *screen, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, uint64_t vram, uint64_t gtt) { vram += cs->used_vram; @@ -1556,7 +1556,7 @@ radeon_cs_memory_below_limit(struct si_screen *screen, * rebuilt. */ static inline void radeon_add_to_buffer_list(struct si_context *sctx, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, struct r600_resource *rbo, enum radeon_bo_usage usage, enum radeon_bo_priority priority) diff --git a/src/gallium/drivers/radeonsi/si_pm4.c b/src/gallium/drivers/radeonsi/si_pm4.c index 4869d19e4d3..446edea49a9 100644 --- a/src/gallium/drivers/radeonsi/si_pm4.c +++ b/src/gallium/drivers/radeonsi/si_pm4.c @@ -123,7 +123,7 @@ void si_pm4_free_state(struct si_context *sctx, void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; for (int i = 0; i < state->nbo; ++i) { radeon_add_to_buffer_list(sctx, sctx->gfx_cs, state->bo[i], diff --git a/src/gallium/drivers/radeonsi/si_query.c b/src/gallium/drivers/radeonsi/si_query.c index 9c51c9892e6..5458e6260fc 100644 --- a/src/gallium/drivers/radeonsi/si_query.c +++ b/src/gallium/drivers/radeonsi/si_query.c @@ -731,7 +731,7 @@ static unsigned event_type_for_stream(unsigned stream) } } -static void emit_sample_streamout(struct radeon_winsys_cs *cs, uint64_t va, +static void emit_sample_streamout(struct radeon_cmdbuf *cs, uint64_t va, unsigned stream) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); @@ -745,7 +745,7 @@ static void si_query_hw_do_emit_start(struct si_context *sctx, struct r600_resource *buffer, uint64_t va) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; switch (query->b.type) { case PIPE_QUERY_OCCLUSION_COUNTER: @@ -829,7 +829,7 @@ static void si_query_hw_do_emit_stop(struct si_context *sctx, struct r600_resource *buffer, uint64_t va) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; uint64_t fence_va = 0; switch (query->b.type) { @@ -920,7 +920,7 @@ static void emit_set_predicate(struct si_context *ctx, struct r600_resource *buf, uint64_t va, uint32_t op) { - struct radeon_winsys_cs *cs = ctx->gfx_cs; + struct radeon_cmdbuf *cs = ctx->gfx_cs; if (ctx->chip_class >= GFX9) { radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 2, 0)); diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index fb4649771fc..92a1d151262 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -66,7 +66,7 @@ static unsigned si_pack_float_12p4(float x) */ static void si_emit_cb_render_state(struct si_context *sctx) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; struct si_state_blend *blend = sctx->queued.named.blend; /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers, * but you never know. */ @@ -703,7 +703,7 @@ static void si_set_blend_color(struct pipe_context *ctx, static void si_emit_blend_color(struct si_context *sctx) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4); radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4); @@ -737,7 +737,7 @@ static void si_set_clip_state(struct pipe_context *ctx, static void si_emit_clip_state(struct si_context *sctx) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4); radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4); @@ -1063,7 +1063,7 @@ static void si_delete_rs_state(struct pipe_context *ctx, void *state) */ static void si_emit_stencil_ref(struct si_context *sctx) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; struct pipe_stencil_ref *ref = &sctx->stencil_ref.state; struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part; @@ -2960,7 +2960,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, static void si_emit_framebuffer_state(struct si_context *sctx) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; struct pipe_framebuffer_state *state = &sctx->framebuffer.state; unsigned i, nr_cbufs = state->nr_cbufs; struct r600_texture *tex = NULL; @@ -3217,7 +3217,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) static void si_emit_msaa_sample_locs(struct si_context *sctx) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; unsigned nr_samples = sctx->framebuffer.nr_samples; bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug; @@ -3330,7 +3330,7 @@ static bool si_out_of_order_rasterization(struct si_context *sctx) static void si_emit_msaa_config(struct si_context *sctx) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes; /* 33% faster rendering to linear color buffers */ bool dst_is_linear = sctx->framebuffer.any_dst_linear; @@ -4302,7 +4302,7 @@ static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask) static void si_emit_sample_mask(struct si_context *sctx) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; unsigned mask = sctx->sample_mask; /* Needed for line and polygon smoothing as well as for the Polaris diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index 5b9d7402019..4a539fc4855 100644 --- a/src/gallium/drivers/radeonsi/si_state.h +++ b/src/gallium/drivers/radeonsi/si_state.h @@ -513,7 +513,7 @@ void si_trace_emit(struct si_context *sctx); /* si_state_msaa.c */ void si_init_msaa_functions(struct si_context *sctx); -void si_emit_sample_locations(struct radeon_winsys_cs *cs, int nr_samples); +void si_emit_sample_locations(struct radeon_cmdbuf *cs, int nr_samples); /* si_state_streamout.c */ void si_streamout_buffers_dirty(struct si_context *sctx); diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index b29135a1e68..2291b4a00ad 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -70,7 +70,7 @@ static bool si_emit_derived_tess_state(struct si_context *sctx, const struct pipe_draw_info *info, unsigned *num_patches) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; struct si_shader *ls_current; struct si_shader_selector *ls; /* The TES pointer will only be used for sctx->last_tcs. @@ -532,7 +532,7 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx, /* rast_prim is the primitive type after GS. */ static bool si_emit_rasterizer_prim_state(struct si_context *sctx) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; enum pipe_prim_type rast_prim = sctx->current_rast_prim; struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; @@ -569,7 +569,7 @@ static void si_emit_vs_state(struct si_context *sctx, } if (sctx->current_vs_state != sctx->last_vs_state) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; radeon_set_sh_reg(cs, sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] + @@ -592,7 +592,7 @@ static void si_emit_draw_registers(struct si_context *sctx, const struct pipe_draw_info *info, unsigned num_patches) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; unsigned prim = si_conv_pipe_prim(info->mode); unsigned ia_multi_vgt_param; @@ -644,7 +644,7 @@ static void si_emit_draw_packets(struct si_context *sctx, unsigned index_offset) { struct pipe_draw_indirect_info *indirect = info->indirect; - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX]; bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off; uint32_t index_max_size = 0; @@ -846,7 +846,7 @@ static void si_emit_draw_packets(struct si_context *sctx, static void si_emit_surface_sync(struct si_context *sctx, unsigned cp_coher_cntl) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; if (sctx->chip_class >= GFX9) { /* Flush caches and wait for the caches to assert idle. */ @@ -869,7 +869,7 @@ static void si_emit_surface_sync(struct si_context *sctx, void si_emit_cache_flush(struct si_context *sctx) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; uint32_t flags = sctx->flags; uint32_t cp_coher_cntl = 0; uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB | @@ -1548,7 +1548,7 @@ void si_draw_rectangle(struct blitter_context *blitter, void si_trace_emit(struct si_context *sctx) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; uint64_t va = sctx->current_saved_cs->trace_buf->gpu_address; uint32_t trace_id = ++sctx->current_saved_cs->trace_id; diff --git a/src/gallium/drivers/radeonsi/si_state_msaa.c b/src/gallium/drivers/radeonsi/si_state_msaa.c index afc98c1465a..10232a5e18b 100644 --- a/src/gallium/drivers/radeonsi/si_state_msaa.c +++ b/src/gallium/drivers/radeonsi/si_state_msaa.c @@ -132,7 +132,7 @@ static void si_get_sample_position(struct pipe_context *ctx, unsigned sample_cou out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f; } -static void si_emit_max_4_sample_locs(struct radeon_winsys_cs *cs, +static void si_emit_max_4_sample_locs(struct radeon_cmdbuf *cs, uint64_t centroid_priority, uint32_t sample_locs) { @@ -145,7 +145,7 @@ static void si_emit_max_4_sample_locs(struct radeon_winsys_cs *cs, radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs); } -static void si_emit_max_16_sample_locs(struct radeon_winsys_cs *cs, +static void si_emit_max_16_sample_locs(struct radeon_cmdbuf *cs, uint64_t centroid_priority, const uint32_t *sample_locs, unsigned num_samples) @@ -161,7 +161,7 @@ static void si_emit_max_16_sample_locs(struct radeon_winsys_cs *cs, radeon_emit_array(cs, sample_locs, num_samples == 8 ? 2 : 4); } -void si_emit_sample_locations(struct radeon_winsys_cs *cs, int nr_samples) +void si_emit_sample_locations(struct radeon_cmdbuf *cs, int nr_samples) { switch (nr_samples) { default: diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index e7610af2fa7..bedd10e784f 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -2626,7 +2626,7 @@ static unsigned si_get_ps_input_cntl(struct si_context *sctx, static void si_emit_spi_map(struct si_context *sctx) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; struct si_shader *ps = sctx->ps_shader.current; struct si_shader *vs = si_get_vs_state(sctx); struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL; @@ -3356,7 +3356,7 @@ bool si_update_shaders(struct si_context *sctx) static void si_emit_scratch_state(struct si_context *sctx) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE, sctx->spi_tmpring_size); diff --git a/src/gallium/drivers/radeonsi/si_state_streamout.c b/src/gallium/drivers/radeonsi/si_state_streamout.c index 67fbb57a6cb..8b0dfa5b116 100644 --- a/src/gallium/drivers/radeonsi/si_state_streamout.c +++ b/src/gallium/drivers/radeonsi/si_state_streamout.c @@ -230,7 +230,7 @@ static void si_set_streamout_targets(struct pipe_context *ctx, static void si_flush_vgt_streamout(struct si_context *sctx) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; unsigned reg_strmout_cntl; /* The register is at different places on different ASICs. */ @@ -256,7 +256,7 @@ static void si_flush_vgt_streamout(struct si_context *sctx) static void si_emit_streamout_begin(struct si_context *sctx) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; struct si_streamout_target **t = sctx->streamout.targets; uint16_t *stride_in_dw = sctx->streamout.stride_in_dw; unsigned i; @@ -311,7 +311,7 @@ static void si_emit_streamout_begin(struct si_context *sctx) void si_emit_streamout_end(struct si_context *sctx) { - struct radeon_winsys_cs *cs = sctx->gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; struct si_streamout_target **t = sctx->streamout.targets; unsigned i; uint64_t va; diff --git a/src/gallium/drivers/radeonsi/si_state_viewport.c b/src/gallium/drivers/radeonsi/si_state_viewport.c index d0287d5ad75..3b16bdcb17f 100644 --- a/src/gallium/drivers/radeonsi/si_state_viewport.c +++ b/src/gallium/drivers/radeonsi/si_state_viewport.c @@ -110,7 +110,7 @@ static void si_scissor_make_union(struct si_signed_scissor *out, } static void si_emit_one_scissor(struct si_context *ctx, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, struct si_signed_scissor *vp_scissor, struct pipe_scissor_state *scissor) { @@ -140,7 +140,7 @@ static void si_emit_guardband(struct si_context *ctx) { const struct si_signed_scissor *vp_as_scissor; struct si_signed_scissor max_vp_scissor; - struct radeon_winsys_cs *cs = ctx->gfx_cs; + struct radeon_cmdbuf *cs = ctx->gfx_cs; struct pipe_viewport_state vp; float left, top, right, bottom, max_range, guardband_x, guardband_y; float discard_x, discard_y; @@ -225,7 +225,7 @@ static void si_emit_guardband(struct si_context *ctx) static void si_emit_scissors(struct si_context *ctx) { - struct radeon_winsys_cs *cs = ctx->gfx_cs; + struct radeon_cmdbuf *cs = ctx->gfx_cs; struct pipe_scissor_state *states = ctx->scissors.states; unsigned mask = ctx->scissors.dirty_mask; bool scissor_enabled = ctx->queued.named.rasterizer->scissor_enable; @@ -287,7 +287,7 @@ static void si_set_viewport_states(struct pipe_context *pctx, static void si_emit_one_viewport(struct si_context *ctx, struct pipe_viewport_state *state) { - struct radeon_winsys_cs *cs = ctx->gfx_cs; + struct radeon_cmdbuf *cs = ctx->gfx_cs; radeon_emit(cs, fui(state->scale[0])); radeon_emit(cs, fui(state->translate[0])); @@ -299,7 +299,7 @@ static void si_emit_one_viewport(struct si_context *ctx, static void si_emit_viewports(struct si_context *ctx) { - struct radeon_winsys_cs *cs = ctx->gfx_cs; + struct radeon_cmdbuf *cs = ctx->gfx_cs; struct pipe_viewport_state *states = ctx->viewports.states; unsigned mask = ctx->viewports.dirty_mask; @@ -341,7 +341,7 @@ si_viewport_zmin_zmax(const struct pipe_viewport_state *vp, bool halfz, static void si_emit_depth_ranges(struct si_context *ctx) { - struct radeon_winsys_cs *cs = ctx->gfx_cs; + struct radeon_cmdbuf *cs = ctx->gfx_cs; struct pipe_viewport_state *states = ctx->viewports.states; unsigned mask = ctx->viewports.depth_range_dirty_mask; bool clip_halfz = ctx->queued.named.rasterizer->clip_halfz; diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c index df8b8292fa0..cd75fe83488 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c @@ -213,7 +213,7 @@ static void amdgpu_bo_destroy_or_cache(struct pb_buffer *_buf) } static void *amdgpu_bo_map(struct pb_buffer *buf, - struct radeon_winsys_cs *rcs, + struct radeon_cmdbuf *rcs, enum pipe_transfer_usage usage) { struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf; diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index eb050b8fdb2..6628ff9f170 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c @@ -260,7 +260,7 @@ static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys *rws, } static struct pipe_fence_handle * -amdgpu_cs_get_next_fence(struct radeon_winsys_cs *rcs) +amdgpu_cs_get_next_fence(struct radeon_cmdbuf *rcs) { struct amdgpu_cs *cs = amdgpu_cs(rcs); struct pipe_fence_handle *fence = NULL; @@ -608,7 +608,7 @@ static int amdgpu_lookup_or_add_sparse_buffer(struct amdgpu_cs *acs, return idx; } -static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs *rcs, +static unsigned amdgpu_cs_add_buffer(struct radeon_cmdbuf *rcs, struct pb_buffer *buf, enum radeon_bo_usage usage, enum radeon_bo_domain domains, @@ -912,7 +912,7 @@ static void amdgpu_destroy_cs_context(struct amdgpu_cs_context *cs) } -static struct radeon_winsys_cs * +static struct radeon_cmdbuf * amdgpu_cs_create(struct radeon_winsys_ctx *rwctx, enum ring_type ring_type, void (*flush)(void *ctx, unsigned flags, @@ -967,12 +967,12 @@ amdgpu_cs_create(struct radeon_winsys_ctx *rwctx, return &cs->main.base; } -static bool amdgpu_cs_validate(struct radeon_winsys_cs *rcs) +static bool amdgpu_cs_validate(struct radeon_cmdbuf *rcs) { return true; } -static bool amdgpu_cs_check_space(struct radeon_winsys_cs *rcs, unsigned dw) +static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw) { struct amdgpu_ib *ib = amdgpu_ib(rcs); struct amdgpu_cs *cs = amdgpu_cs_from_ib(ib); @@ -996,7 +996,7 @@ static bool amdgpu_cs_check_space(struct radeon_winsys_cs *rcs, unsigned dw) /* Allocate a new chunk */ if (rcs->num_prev >= rcs->max_prev) { unsigned new_max_prev = MAX2(1, 2 * rcs->max_prev); - struct radeon_winsys_cs_chunk *new_prev; + struct radeon_cmdbuf_chunk *new_prev; new_prev = REALLOC(rcs->prev, sizeof(*new_prev) * rcs->max_prev, @@ -1053,7 +1053,7 @@ static bool amdgpu_cs_check_space(struct radeon_winsys_cs *rcs, unsigned dw) return true; } -static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs *rcs, +static unsigned amdgpu_cs_get_buffer_list(struct radeon_cmdbuf *rcs, struct radeon_bo_list_item *list) { struct amdgpu_cs_context *cs = amdgpu_cs(rcs)->csc; @@ -1102,7 +1102,7 @@ static bool is_noop_fence_dependency(struct amdgpu_cs *acs, return amdgpu_fence_wait((void *)fence, 0, false); } -static void amdgpu_cs_add_fence_dependency(struct radeon_winsys_cs *rws, +static void amdgpu_cs_add_fence_dependency(struct radeon_cmdbuf *rws, struct pipe_fence_handle *pfence) { struct amdgpu_cs *acs = amdgpu_cs(rws); @@ -1236,7 +1236,7 @@ static unsigned add_syncobj_to_signal_entry(struct amdgpu_cs_context *cs) return idx; } -static void amdgpu_cs_add_syncobj_signal(struct radeon_winsys_cs *rws, +static void amdgpu_cs_add_syncobj_signal(struct radeon_cmdbuf *rws, struct pipe_fence_handle *fence) { struct amdgpu_cs *acs = amdgpu_cs(rws); @@ -1514,7 +1514,7 @@ cleanup: } /* Make sure the previous submission is completed. */ -void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs) +void amdgpu_cs_sync_flush(struct radeon_cmdbuf *rcs) { struct amdgpu_cs *cs = amdgpu_cs(rcs); @@ -1522,7 +1522,7 @@ void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs) util_queue_fence_wait(&cs->flush_completed); } -static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs, +static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs, unsigned flags, struct pipe_fence_handle **fence) { @@ -1639,7 +1639,7 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs, return error_code; } -static void amdgpu_cs_destroy(struct radeon_winsys_cs *rcs) +static void amdgpu_cs_destroy(struct radeon_cmdbuf *rcs) { struct amdgpu_cs *cs = amdgpu_cs(rcs); @@ -1654,7 +1654,7 @@ static void amdgpu_cs_destroy(struct radeon_winsys_cs *rcs) FREE(cs); } -static bool amdgpu_bo_is_referenced(struct radeon_winsys_cs *rcs, +static bool amdgpu_bo_is_referenced(struct radeon_cmdbuf *rcs, struct pb_buffer *_buf, enum radeon_bo_usage usage) { diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h index 80acb7cb8c2..5f96193750b 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h @@ -61,7 +61,7 @@ enum ib_type { }; struct amdgpu_ib { - struct radeon_winsys_cs base; + struct radeon_cmdbuf base; /* A buffer out of which new IBs are allocated. */ struct pb_buffer *big_ib_buffer; @@ -193,13 +193,13 @@ static inline void amdgpu_fence_reference(struct pipe_fence_handle **dst, int amdgpu_lookup_buffer(struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo *bo); static inline struct amdgpu_ib * -amdgpu_ib(struct radeon_winsys_cs *base) +amdgpu_ib(struct radeon_cmdbuf *base) { return (struct amdgpu_ib *)base; } static inline struct amdgpu_cs * -amdgpu_cs(struct radeon_winsys_cs *base) +amdgpu_cs(struct radeon_cmdbuf *base) { assert(amdgpu_ib(base)->ib_type == IB_MAIN); return (struct amdgpu_cs*)base; @@ -261,7 +261,7 @@ bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout, void amdgpu_add_fences(struct amdgpu_winsys_bo *bo, unsigned num_fences, struct pipe_fence_handle **fences); -void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs); +void amdgpu_cs_sync_flush(struct radeon_cmdbuf *rcs); void amdgpu_cs_init_functions(struct amdgpu_winsys *ws); void amdgpu_cs_submit_ib(void *job, int thread_index); diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c index caa799195fb..69202dc7e77 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c @@ -101,7 +101,7 @@ static void amdgpu_winsys_query_info(struct radeon_winsys *rws, *info = ((struct amdgpu_winsys *)rws)->info; } -static bool amdgpu_cs_request_feature(struct radeon_winsys_cs *rcs, +static bool amdgpu_cs_request_feature(struct radeon_cmdbuf *rcs, enum radeon_feature_id fid, bool enable) { diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c index 93ab4791c55..07a9b2d758e 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c @@ -497,7 +497,7 @@ void *radeon_bo_do_map(struct radeon_bo *bo) } static void *radeon_bo_map(struct pb_buffer *buf, - struct radeon_winsys_cs *rcs, + struct radeon_cmdbuf *rcs, enum pipe_transfer_usage usage) { struct radeon_bo *bo = (struct radeon_bo*)buf; diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c index 9070464bec8..90386027235 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c @@ -67,7 +67,7 @@ #define RELOC_DWORDS (sizeof(struct drm_radeon_cs_reloc) / sizeof(uint32_t)) static struct pipe_fence_handle * -radeon_cs_create_fence(struct radeon_winsys_cs *rcs); +radeon_cs_create_fence(struct radeon_cmdbuf *rcs); static void radeon_fence_reference(struct pipe_fence_handle **dst, struct pipe_fence_handle *src); @@ -145,7 +145,7 @@ static void radeon_destroy_cs_context(struct radeon_cs_context *csc) } -static struct radeon_winsys_cs * +static struct radeon_cmdbuf * radeon_drm_cs_create(struct radeon_winsys_ctx *ctx, enum ring_type ring_type, void (*flush)(void *ctx, unsigned flags, @@ -329,7 +329,7 @@ static int radeon_lookup_or_add_slab_buffer(struct radeon_drm_cs *cs, return idx; } -static unsigned radeon_drm_cs_add_buffer(struct radeon_winsys_cs *rcs, +static unsigned radeon_drm_cs_add_buffer(struct radeon_cmdbuf *rcs, struct pb_buffer *buf, enum radeon_bo_usage usage, enum radeon_bo_domain domains, @@ -376,7 +376,7 @@ static unsigned radeon_drm_cs_add_buffer(struct radeon_winsys_cs *rcs, return index; } -static int radeon_drm_cs_lookup_buffer(struct radeon_winsys_cs *rcs, +static int radeon_drm_cs_lookup_buffer(struct radeon_cmdbuf *rcs, struct pb_buffer *buf) { struct radeon_drm_cs *cs = radeon_drm_cs(rcs); @@ -384,7 +384,7 @@ static int radeon_drm_cs_lookup_buffer(struct radeon_winsys_cs *rcs, return radeon_lookup_buffer(cs->csc, (struct radeon_bo*)buf); } -static bool radeon_drm_cs_validate(struct radeon_winsys_cs *rcs) +static bool radeon_drm_cs_validate(struct radeon_cmdbuf *rcs) { struct radeon_drm_cs *cs = radeon_drm_cs(rcs); bool status = @@ -423,13 +423,13 @@ static bool radeon_drm_cs_validate(struct radeon_winsys_cs *rcs) return status; } -static bool radeon_drm_cs_check_space(struct radeon_winsys_cs *rcs, unsigned dw) +static bool radeon_drm_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw) { assert(rcs->current.cdw <= rcs->current.max_dw); return rcs->current.max_dw - rcs->current.cdw >= dw; } -static unsigned radeon_drm_cs_get_buffer_list(struct radeon_winsys_cs *rcs, +static unsigned radeon_drm_cs_get_buffer_list(struct radeon_cmdbuf *rcs, struct radeon_bo_list_item *list) { struct radeon_drm_cs *cs = radeon_drm_cs(rcs); @@ -480,7 +480,7 @@ void radeon_drm_cs_emit_ioctl_oneshot(void *job, int thread_index) /* * Make sure previous submission of this cs are completed */ -void radeon_drm_cs_sync_flush(struct radeon_winsys_cs *rcs) +void radeon_drm_cs_sync_flush(struct radeon_cmdbuf *rcs) { struct radeon_drm_cs *cs = radeon_drm_cs(rcs); @@ -541,7 +541,7 @@ static void radeon_bo_slab_fence(struct radeon_bo *bo, struct radeon_bo *fence) DEBUG_GET_ONCE_BOOL_OPTION(noop, "RADEON_NOOP", false) -static int radeon_drm_cs_flush(struct radeon_winsys_cs *rcs, +static int radeon_drm_cs_flush(struct radeon_cmdbuf *rcs, unsigned flags, struct pipe_fence_handle **pfence) { @@ -700,7 +700,7 @@ static int radeon_drm_cs_flush(struct radeon_winsys_cs *rcs, return 0; } -static void radeon_drm_cs_destroy(struct radeon_winsys_cs *rcs) +static void radeon_drm_cs_destroy(struct radeon_cmdbuf *rcs) { struct radeon_drm_cs *cs = radeon_drm_cs(rcs); @@ -715,7 +715,7 @@ static void radeon_drm_cs_destroy(struct radeon_winsys_cs *rcs) FREE(cs); } -static bool radeon_bo_is_referenced(struct radeon_winsys_cs *rcs, +static bool radeon_bo_is_referenced(struct radeon_cmdbuf *rcs, struct pb_buffer *_buf, enum radeon_bo_usage usage) { @@ -744,7 +744,7 @@ static bool radeon_bo_is_referenced(struct radeon_winsys_cs *rcs, /* FENCES */ static struct pipe_fence_handle * -radeon_cs_create_fence(struct radeon_winsys_cs *rcs) +radeon_cs_create_fence(struct radeon_cmdbuf *rcs) { struct radeon_drm_cs *cs = radeon_drm_cs(rcs); struct pb_buffer *fence; @@ -777,7 +777,7 @@ static void radeon_fence_reference(struct pipe_fence_handle **dst, } static struct pipe_fence_handle * -radeon_drm_cs_get_next_fence(struct radeon_winsys_cs *rcs) +radeon_drm_cs_get_next_fence(struct radeon_cmdbuf *rcs) { struct radeon_drm_cs *cs = radeon_drm_cs(rcs); struct pipe_fence_handle *fence = NULL; @@ -796,7 +796,7 @@ radeon_drm_cs_get_next_fence(struct radeon_winsys_cs *rcs) } static void -radeon_drm_cs_add_fence_dependency(struct radeon_winsys_cs *cs, +radeon_drm_cs_add_fence_dependency(struct radeon_cmdbuf *cs, struct pipe_fence_handle *fence) { /* TODO: Handle the following unlikely multi-threaded scenario: diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h index f9b26af28fa..75fb09bd001 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h +++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h @@ -65,7 +65,7 @@ struct radeon_cs_context { }; struct radeon_drm_cs { - struct radeon_winsys_cs base; + struct radeon_cmdbuf base; enum ring_type ring_type; /* We flip between these two CS. While one is being consumed @@ -92,7 +92,7 @@ struct radeon_drm_cs { int radeon_lookup_buffer(struct radeon_cs_context *csc, struct radeon_bo *bo); static inline struct radeon_drm_cs * -radeon_drm_cs(struct radeon_winsys_cs *base) +radeon_drm_cs(struct radeon_cmdbuf *base) { return (struct radeon_drm_cs*)base; } @@ -131,7 +131,7 @@ radeon_bo_is_referenced_by_any_cs(struct radeon_bo *bo) return bo->num_cs_references != 0; } -void radeon_drm_cs_sync_flush(struct radeon_winsys_cs *rcs); +void radeon_drm_cs_sync_flush(struct radeon_cmdbuf *rcs); void radeon_drm_cs_init_functions(struct radeon_drm_winsys *ws); void radeon_drm_cs_emit_ioctl_oneshot(void *job, int thread_index); diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index 86df2ac055e..c02f596f637 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -621,7 +621,7 @@ static void radeon_query_info(struct radeon_winsys *rws, *info = ((struct radeon_drm_winsys *)rws)->info; } -static bool radeon_cs_request_feature(struct radeon_winsys_cs *rcs, +static bool radeon_cs_request_feature(struct radeon_cmdbuf *rcs, enum radeon_feature_id fid, bool enable) { |