3 files changed, 5 insertions, 2 deletions
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index c65bb204242..57d12139233 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -8755,7 +8755,8 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
 
    /* Currently, the compiler only supports SIMD32 on SNB+ */
    if (v8->max_dispatch_width >= 32 && !use_rep_send &&
-       devinfo->gen >= 6 && simd16_cfg) {
+       devinfo->gen >= 6 && simd16_cfg &&
+       !(INTEL_DEBUG & DEBUG_NO32)) {
       /* Try a SIMD32 compile */
       v32 = new fs_visitor(compiler, log_data, mem_ctx, &key->base,
                            &prog_data->base, shader, 32, shader_time_index32);
diff --git a/src/intel/dev/gen_debug.c b/src/intel/dev/gen_debug.c
index ffed3045485..4e610dc4169 100644
--- a/src/intel/dev/gen_debug.c
+++ b/src/intel/dev/gen_debug.c
@@ -90,6 +90,7 @@ static const struct debug_control debug_control[] = {
    { "bt",          DEBUG_BT },
    { "pc",          DEBUG_PIPE_CONTROL },
    { "nofc",        DEBUG_NO_FAST_CLEAR },
+   { "no32",        DEBUG_NO32 },
    { NULL,    0 }
 };
 
diff --git a/src/intel/dev/gen_debug.h b/src/intel/dev/gen_debug.h
index 5c3e100e8de..aff96ae3fa2 100644
--- a/src/intel/dev/gen_debug.h
+++ b/src/intel/dev/gen_debug.h
@@ -88,6 +88,7 @@ extern uint64_t INTEL_DEBUG;
 #define DEBUG_BT                  (1ull << 44)
 #define DEBUG_PIPE_CONTROL        (1ull << 45)
 #define DEBUG_NO_FAST_CLEAR       (1ull << 46)
+#define DEBUG_NO32                (1ull << 47)
 
 /* These flags are not compatible with the disk shader cache */
 #define DEBUG_DISK_CACHE_DISABLE_MASK DEBUG_SHADER_TIME
@@ -96,7 +97,7 @@ extern uint64_t INTEL_DEBUG;
 #define DEBUG_DISK_CACHE_MASK \
    (DEBUG_NO16 | DEBUG_NO_DUAL_OBJECT_GS | DEBUG_NO8 |  DEBUG_SPILL_FS | \
    DEBUG_SPILL_VEC4 | DEBUG_NO_COMPACTION | DEBUG_DO32 | DEBUG_SOFT64 | \
-   DEBUG_TCS_EIGHT_PATCH)
+   DEBUG_TCS_EIGHT_PATCH | DEBUG_NO32)
 
 #ifdef HAVE_ANDROID_PLATFORM
 #define LOG_TAG "INTEL-MESA"