diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/intel/compiler/brw_eu.c | 14 | ||||
| -rw-r--r-- | src/intel/compiler/brw_eu.h | 6 | ||||
| -rw-r--r-- | src/intel/compiler/brw_vec4_generator.cpp | 2 | ||||
| -rw-r--r-- | src/intel/compiler/test_eu_compact.cpp | 4 |
4 files changed, 13 insertions, 13 deletions
diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c index db08999c7ee..fbc899d765e 100644 --- a/src/intel/compiler/brw_eu.c +++ b/src/intel/compiler/brw_eu.c @@ -41,7 +41,7 @@ /* Returns a conditional modifier that negates the condition. */ enum brw_conditional_mod -brw_negate_cmod(uint32_t cmod) +brw_negate_cmod(enum brw_conditional_mod cmod) { switch (cmod) { case BRW_CONDITIONAL_Z: @@ -57,7 +57,7 @@ brw_negate_cmod(uint32_t cmod) case BRW_CONDITIONAL_LE: return BRW_CONDITIONAL_G; default: - return ~0; + unreachable("Can't negate this cmod"); } } @@ -65,7 +65,7 @@ brw_negate_cmod(uint32_t cmod) * src1 in e.g. CMP. */ enum brw_conditional_mod -brw_swap_cmod(uint32_t cmod) +brw_swap_cmod(enum brw_conditional_mod cmod) { switch (cmod) { case BRW_CONDITIONAL_Z: @@ -152,7 +152,7 @@ brw_set_default_exec_size(struct brw_codegen *p, unsigned value) p->current->exec_size = value; } -void brw_set_default_predicate_control( struct brw_codegen *p, unsigned pc ) +void brw_set_default_predicate_control(struct brw_codegen *p, enum brw_predicate pc) { p->current->predicate = pc; } @@ -379,7 +379,7 @@ bool brw_try_override_assembly(struct brw_codegen *p, int start_offset, p->next_insn_offset = start_offset + sb.st_size; p->store_size = (start_offset + sb.st_size) / sizeof(brw_inst); - p->store = reralloc_size(p->mem_ctx, p->store, p->next_insn_offset); + p->store = (brw_inst *)reralloc_size(p->mem_ctx, p->store, p->next_insn_offset); assert(p->store); read(fd, p->store + start_offset, sb.st_size); @@ -400,14 +400,14 @@ brw_disassemble(const struct gen_device_info *devinfo, bool dump_hex = (INTEL_DEBUG & DEBUG_HEX) != 0; for (int offset = start; offset < end;) { - const brw_inst *insn = assembly + offset; + const brw_inst *insn = (const brw_inst *)((char *)assembly + offset); brw_inst uncompacted; bool compacted = brw_inst_cmpt_control(devinfo, insn); if (0) fprintf(out, "0x%08x: ", offset); if (compacted) { - brw_compact_inst *compacted = (void *)insn; + brw_compact_inst *compacted = (brw_compact_inst *)insn; if (dump_hex) { unsigned char * insn_ptr = ((unsigned char *)&insn[0]); const unsigned int blank_spaces = 24; diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h index 306c24a4e4f..ef2cf889cd1 100644 --- a/src/intel/compiler/brw_eu.h +++ b/src/intel/compiler/brw_eu.h @@ -150,7 +150,7 @@ void brw_inst_set_group(const struct gen_device_info *devinfo, brw_inst *inst, unsigned group); void brw_set_default_group(struct brw_codegen *p, unsigned group); void brw_set_default_compression_control(struct brw_codegen *p, enum brw_compression c); -void brw_set_default_predicate_control( struct brw_codegen *p, unsigned pc ); +void brw_set_default_predicate_control(struct brw_codegen *p, enum brw_predicate pc); void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse); void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg); void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value); @@ -1189,8 +1189,8 @@ brw_set_desc(struct brw_codegen *p, brw_inst *insn, unsigned desc) void brw_set_uip_jip(struct brw_codegen *p, int start_offset); -enum brw_conditional_mod brw_negate_cmod(uint32_t cmod); -enum brw_conditional_mod brw_swap_cmod(uint32_t cmod); +enum brw_conditional_mod brw_negate_cmod(enum brw_conditional_mod cmod); +enum brw_conditional_mod brw_swap_cmod(enum brw_conditional_mod cmod); /* brw_eu_compact.c */ void brw_init_compaction_tables(const struct gen_device_info *devinfo); diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp index e6842e47c8f..39ddd8a0ddc 100644 --- a/src/intel/compiler/brw_vec4_generator.cpp +++ b/src/intel/compiler/brw_vec4_generator.cpp @@ -1208,7 +1208,7 @@ generate_scratch_write(struct brw_codegen *p, /* If the instruction is predicated, we'll predicate the send, not * the header setup. */ - brw_set_default_predicate_control(p, false); + brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); gen6_resolve_implied_move(p, &header, inst->base_mrf); diff --git a/src/intel/compiler/test_eu_compact.cpp b/src/intel/compiler/test_eu_compact.cpp index f6924abd368..702762c194a 100644 --- a/src/intel/compiler/test_eu_compact.cpp +++ b/src/intel/compiler/test_eu_compact.cpp @@ -243,7 +243,7 @@ gen_f0_0_MOV_GRF_GRF(struct brw_codegen *p) struct brw_reg g2 = brw_vec8_grf(2, 0); brw_push_insn_state(p); - brw_set_default_predicate_control(p, true); + brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL); brw_MOV(p, g0, g2); brw_pop_insn_state(p); } @@ -259,7 +259,7 @@ gen_f0_1_MOV_GRF_GRF(struct brw_codegen *p) struct brw_reg g2 = brw_vec8_grf(2, 0); brw_push_insn_state(p); - brw_set_default_predicate_control(p, true); + brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL); brw_inst *mov = brw_MOV(p, g0, g2); brw_inst_set_flag_subreg_nr(p->devinfo, mov, 1); brw_pop_insn_state(p); |