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-rw-r--r--src/compiler/nir/nir.h10
-rw-r--r--src/intel/compiler/brw_compiler.c1
2 files changed, 11 insertions, 0 deletions
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 4fa50940e17..bc7ae1cc03e 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -2630,6 +2630,16 @@ typedef struct nir_shader_compiler_options {
/* Lowers when rotate instruction is not supported */
bool lower_rotate;
+ /**
+ * Is this the Intel vec4 backend?
+ *
+ * Used to inhibit algebraic optimizations that are known to be harmful on
+ * the Intel vec4 backend. This is generally applicable to any
+ * optimization that might cause more immediate values to be used in
+ * 3-source (e.g., ffma and flrp) instructions.
+ */
+ bool intel_vec4;
+
unsigned max_unroll_iterations;
nir_lower_int64_options lower_int64_options;
diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c
index eb1f3808fbc..3a80f807b87 100644
--- a/src/intel/compiler/brw_compiler.c
+++ b/src/intel/compiler/brw_compiler.c
@@ -82,6 +82,7 @@ static const struct nir_shader_compiler_options vector_nir_options = {
.lower_unpack_unorm_2x16 = true,
.lower_extract_byte = true,
.lower_extract_word = true,
+ .intel_vec4 = true,
.max_unroll_iterations = 32,
};