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-rw-r--r--src/gallium/winsys/r600/drm/r600_drm.c91
-rw-r--r--src/gallium/winsys/r600/drm/r600_hw_context.c2
-rw-r--r--src/gallium/winsys/r600/drm/r600_priv.h6
-rw-r--r--src/gallium/winsys/r600/drm/radeon_bo.c18
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_drm_winsys.c32
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_winsys.h2
6 files changed, 51 insertions, 100 deletions
diff --git a/src/gallium/winsys/r600/drm/r600_drm.c b/src/gallium/winsys/r600/drm/r600_drm.c
index 325547ab4ec..ab15257efb2 100644
--- a/src/gallium/winsys/r600/drm/r600_drm.c
+++ b/src/gallium/winsys/r600/drm/r600_drm.c
@@ -76,12 +76,12 @@ struct r600_tiling_info *r600_get_tiling_info(struct radeon *radeon)
unsigned r600_get_clock_crystal_freq(struct radeon *radeon)
{
- return radeon->clock_crystal_freq;
+ return radeon->info.r600_clock_crystal_freq;
}
unsigned r600_get_num_backends(struct radeon *radeon)
{
- return radeon->num_backends;
+ return radeon->info.r600_num_backends;
}
unsigned r600_get_num_tile_pipes(struct radeon *radeon)
@@ -96,7 +96,7 @@ unsigned r600_get_backend_map(struct radeon *radeon)
unsigned r600_get_minor_version(struct radeon *radeon)
{
- return radeon->minor_version;
+ return radeon->info.drm_minor;
}
static int r600_interpret_tiling(struct radeon *radeon, uint32_t tiling_config)
@@ -191,59 +191,16 @@ static int eg_interpret_tiling(struct radeon *radeon, uint32_t tiling_config)
static int radeon_drm_get_tiling(struct radeon *radeon)
{
- struct drm_radeon_info info = {};
- int r;
- uint32_t tiling_config = 0;
-
- info.request = RADEON_INFO_TILING_CONFIG;
- info.value = (uintptr_t)&tiling_config;
- r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info,
- sizeof(struct drm_radeon_info));
+ uint32_t tiling_config = radeon->info.r600_tiling_config;
- if (r)
+ if (!tiling_config)
return 0;
if (radeon->chip_class == R600 || radeon->chip_class == R700) {
- r = r600_interpret_tiling(radeon, tiling_config);
+ return r600_interpret_tiling(radeon, tiling_config);
} else {
- r = eg_interpret_tiling(radeon, tiling_config);
+ return eg_interpret_tiling(radeon, tiling_config);
}
- return r;
-}
-
-static int radeon_get_clock_crystal_freq(struct radeon *radeon)
-{
- struct drm_radeon_info info = {};
- uint32_t clock_crystal_freq = 0;
- int r;
-
- info.request = RADEON_INFO_CLOCK_CRYSTAL_FREQ;
- info.value = (uintptr_t)&clock_crystal_freq;
- r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info,
- sizeof(struct drm_radeon_info));
- if (r)
- return r;
-
- radeon->clock_crystal_freq = clock_crystal_freq;
- return 0;
-}
-
-
-static int radeon_get_num_backends(struct radeon *radeon)
-{
- struct drm_radeon_info info = {};
- uint32_t num_backends = 0;
- int r;
-
- info.request = RADEON_INFO_NUM_BACKENDS;
- info.value = (uintptr_t)&num_backends;
- r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info,
- sizeof(struct drm_radeon_info));
- if (r)
- return r;
-
- radeon->num_backends = num_backends;
- return 0;
}
static int radeon_get_num_tile_pipes(struct radeon *radeon)
@@ -254,7 +211,7 @@ static int radeon_get_num_tile_pipes(struct radeon *radeon)
info.request = RADEON_INFO_NUM_TILE_PIPES;
info.value = (uintptr_t)&num_tile_pipes;
- r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info,
+ r = drmCommandWriteRead(radeon->info.fd, DRM_RADEON_INFO, &info,
sizeof(struct drm_radeon_info));
if (r)
return r;
@@ -271,7 +228,7 @@ static int radeon_get_backend_map(struct radeon *radeon)
info.request = RADEON_INFO_BACKEND_MAP;
info.value = (uintptr_t)&backend_map;
- r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info,
+ r = drmCommandWriteRead(radeon->info.fd, DRM_RADEON_INFO, &info,
sizeof(struct drm_radeon_info));
if (r)
return r;
@@ -282,7 +239,6 @@ static int radeon_get_backend_map(struct radeon *radeon)
return 0;
}
-
static int radeon_init_fence(struct radeon *radeon)
{
radeon->fence = 1;
@@ -307,7 +263,7 @@ static int handle_compare(void *key1, void *key2)
return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
}
-static struct radeon *radeon_new(struct radeon_winsys *rw)
+struct radeon *r600_drm_winsys_create(struct radeon_winsys *rw)
{
struct radeon *radeon;
int r;
@@ -318,15 +274,10 @@ static struct radeon *radeon_new(struct radeon_winsys *rw)
}
rw->query_info(rw, &radeon->info);
- radeon->fd = radeon->info.fd;
- radeon->device = radeon->info.pci_id;
- radeon->num_backends = radeon->info.r600_num_backends;
- radeon->refcount = 1;
- radeon->minor_version = radeon->info.drm_minor;
- radeon->family = radeon_family_from_device(radeon->device);
+ radeon->family = radeon_family_from_device(radeon->info.pci_id);
if (radeon->family == CHIP_UNKNOWN) {
- fprintf(stderr, "Unknown chipset 0x%04X\n", radeon->device);
+ fprintf(stderr, "Unknown chipset 0x%04X\n", radeon->info.pci_id);
return radeon_decref(radeon);
}
/* setup class */
@@ -373,20 +324,14 @@ static struct radeon *radeon_new(struct radeon_winsys *rw)
break;
default:
fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n",
- __func__, radeon->device);
+ __func__, radeon->info.pci_id);
break;
}
if (radeon_drm_get_tiling(radeon))
return NULL;
- /* get the GPU counter frequency, failure is non fatal */
- radeon_get_clock_crystal_freq(radeon);
-
- if (radeon->minor_version >= 9)
- radeon_get_num_backends(radeon);
-
- if (radeon->minor_version >= 11) {
+ if (radeon->info.drm_minor >= 11) {
radeon_get_num_tile_pipes(radeon);
radeon_get_backend_map(radeon);
}
@@ -406,18 +351,10 @@ static struct radeon *radeon_new(struct radeon_winsys *rw)
return radeon;
}
-struct radeon *r600_drm_winsys_create(struct radeon_winsys *rw)
-{
- return radeon_new(rw);
-}
-
struct radeon *radeon_decref(struct radeon *radeon)
{
if (radeon == NULL)
return NULL;
- if (--radeon->refcount > 0) {
- return NULL;
- }
util_hash_table_destroy(radeon->bo_handles);
pipe_mutex_destroy(radeon->bo_handles_mutex);
diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c
index 30af4e8066f..46ca4ed907a 100644
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -1621,7 +1621,7 @@ void r600_context_flush(struct r600_context *ctx)
chunks[1].chunk_data = (uint64_t)(uintptr_t)ctx->reloc;
chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0];
chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1];
- r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib,
+ r = drmCommandWriteRead(ctx->radeon->info.fd, DRM_RADEON_CS, &drmib,
sizeof(struct drm_radeon_cs));
if (r) {
fprintf(stderr, "radeon: The kernel rejected CS, "
diff --git a/src/gallium/winsys/r600/drm/r600_priv.h b/src/gallium/winsys/r600/drm/r600_priv.h
index 7630b30b5f0..9fc7c534646 100644
--- a/src/gallium/winsys/r600/drm/r600_priv.h
+++ b/src/gallium/winsys/r600/drm/r600_priv.h
@@ -45,9 +45,6 @@ struct r600_bo;
struct radeon {
struct radeon_info info;
- int fd;
- int refcount;
- unsigned device;
unsigned family;
enum chip_class chip_class;
struct r600_tiling_info tiling_info;
@@ -55,12 +52,9 @@ struct radeon {
unsigned fence;
unsigned *cfence;
struct r600_bo *fence_bo;
- unsigned clock_crystal_freq;
- unsigned num_backends;
unsigned num_tile_pipes;
unsigned backend_map;
boolean backend_map_valid;
- unsigned minor_version;
/* List of buffer handles and its mutex. */
struct util_hash_table *bo_handles;
diff --git a/src/gallium/winsys/r600/drm/radeon_bo.c b/src/gallium/winsys/r600/drm/radeon_bo.c
index 45cf6f09671..34696da515b 100644
--- a/src/gallium/winsys/r600/drm/radeon_bo.c
+++ b/src/gallium/winsys/r600/drm/radeon_bo.c
@@ -44,14 +44,14 @@ int radeon_bo_fixed_map(struct radeon *radeon, struct radeon_bo *bo)
args.handle = bo->handle;
args.offset = 0;
args.size = (uint64_t)bo->size;
- r = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_MMAP,
+ r = drmCommandWriteRead(radeon->info.fd, DRM_RADEON_GEM_MMAP,
&args, sizeof(args));
if (r) {
fprintf(stderr, "error mapping %p 0x%08X (error = %d)\n",
bo, bo->handle, r);
return r;
}
- ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, radeon->fd, args.addr_ptr);
+ ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, radeon->info.fd, args.addr_ptr);
if (ptr == MAP_FAILED) {
fprintf(stderr, "%s failed to map bo\n", __func__);
return -errno;
@@ -101,7 +101,7 @@ struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
memset(&open_arg, 0, sizeof(open_arg));
open_arg.name = handle;
- r = drmIoctl(radeon->fd, DRM_IOCTL_GEM_OPEN, &open_arg);
+ r = drmIoctl(radeon->info.fd, DRM_IOCTL_GEM_OPEN, &open_arg);
if (r != 0) {
free(bo);
return NULL;
@@ -118,7 +118,7 @@ struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
args.initial_domain = initial_domain;
args.flags = 0;
args.handle = 0;
- r = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_CREATE,
+ r = drmCommandWriteRead(radeon->info.fd, DRM_RADEON_GEM_CREATE,
&args, sizeof(args));
bo->handle = args.handle;
if (r) {
@@ -153,7 +153,7 @@ static void radeon_bo_destroy(struct radeon *radeon, struct radeon_bo *bo)
radeon_bo_fixed_unmap(radeon, bo);
memset(&args, 0, sizeof(args));
args.handle = bo->handle;
- drmIoctl(radeon->fd, DRM_IOCTL_GEM_CLOSE, &args);
+ drmIoctl(radeon->info.fd, DRM_IOCTL_GEM_CLOSE, &args);
memset(bo, 0, sizeof(struct radeon_bo));
free(bo);
}
@@ -188,7 +188,7 @@ int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo)
memset(&args, 0, sizeof(args));
args.handle = bo->handle;
do {
- ret = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_WAIT_IDLE,
+ ret = drmCommandWriteRead(radeon->info.fd, DRM_RADEON_GEM_WAIT_IDLE,
&args, sizeof(args));
} while (ret == -EBUSY);
return ret;
@@ -213,7 +213,7 @@ int radeon_bo_busy(struct radeon *radeon, struct radeon_bo *bo, uint32_t *domain
args.handle = bo->handle;
args.domain = 0;
- ret = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_BUSY,
+ ret = drmCommandWriteRead(radeon->info.fd, DRM_RADEON_GEM_BUSY,
&args, sizeof(args));
*domain = args.domain;
@@ -229,7 +229,7 @@ int radeon_bo_get_tiling_flags(struct radeon *radeon,
int ret;
args.handle = bo->handle;
- ret = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_GET_TILING,
+ ret = drmCommandWriteRead(radeon->info.fd, DRM_RADEON_GEM_GET_TILING,
&args, sizeof(args));
if (ret)
return ret;
@@ -247,7 +247,7 @@ int radeon_bo_get_name(struct radeon *radeon,
int ret;
flink.handle = bo->handle;
- ret = drmIoctl(radeon->fd, DRM_IOCTL_GEM_FLINK, &flink);
+ ret = drmIoctl(radeon->info.fd, DRM_IOCTL_GEM_FLINK, &flink);
if (ret)
return ret;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index faeb66c8908..3be6e34f6f0 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -41,12 +41,22 @@
#include <xf86drm.h>
#include <stdio.h>
+#ifndef RADEON_INFO_TILING_CONFIG
+#define RADEON_INFO_TILING_CONFIG 6
+#endif
+
#ifndef RADEON_INFO_WANT_HYPERZ
#define RADEON_INFO_WANT_HYPERZ 7
#endif
+
#ifndef RADEON_INFO_WANT_CMASK
#define RADEON_INFO_WANT_CMASK 8
#endif
+
+#ifndef RADEON_INFO_CLOCK_CRYSTAL_FREQ
+#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 9
+#endif
+
#ifndef RADEON_INFO_NUM_BACKENDS
#define RADEON_INFO_NUM_BACKENDS 10
#endif
@@ -107,7 +117,7 @@ static boolean radeon_set_fd_access(struct radeon_drm_cs *applier,
}
static boolean radeon_get_drm_value(int fd, unsigned request,
- const char *name, uint32_t *out)
+ const char *errname, uint32_t *out)
{
struct drm_radeon_info info = {0};
int retval;
@@ -116,9 +126,9 @@ static boolean radeon_get_drm_value(int fd, unsigned request,
info.request = request;
retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
- if (retval) {
- fprintf(stderr, "%s: Failed to get %s, error number %d\n",
- __func__, name, retval);
+ if (retval && errname) {
+ fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
+ errname, retval);
return FALSE;
}
return TRUE;
@@ -196,8 +206,8 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
&gem_info, sizeof(gem_info));
if (retval) {
- fprintf(stderr, "%s: Failed to get MM info, error number %d\n",
- __FUNCTION__, retval);
+ fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
+ retval);
return FALSE;
}
ws->info.gart_size = gem_info.gart_size;
@@ -218,10 +228,18 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
return FALSE;
}
else if (ws->gen == R600) {
- if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
+ if (ws->info.drm_minor >= 9 &&
+ !radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
"num backends",
&ws->info.r600_num_backends))
return FALSE;
+
+ /* get the GPU counter frequency, failure is not fatal */
+ radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
+ &ws->info.r600_clock_crystal_freq);
+
+ radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
+ &ws->info.r600_tiling_config);
}
return TRUE;
diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h
index 2a49e615981..2948ea78c18 100644
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -83,6 +83,8 @@ struct radeon_info {
uint32_t r300_num_z_pipes;
uint32_t r600_num_backends;
+ uint32_t r600_clock_crystal_freq;
+ uint32_t r600_tiling_config;
};
enum radeon_feature_id {
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 13:39:30 +0000