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-rw-r--r--src/mesa/drivers/dri/i965/brw_vs_state.c9
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_state.c10
2 files changed, 17 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c
index 54ff754b1dd..4dda5224042 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_state.c
@@ -55,7 +55,14 @@ brw_upload_vs_unit(struct brw_context *brw)
brw->vs.prog_offset +
(vs->thread0.grf_reg_count << 1)) >> 6;
- vs->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
+ /* Use ALT floating point mode for ARB vertex programs, because they
+ * require 0^0 == 1.
+ */
+ if (brw->ctx.Shader.CurrentVertexProgram == NULL)
+ vs->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
+ else
+ vs->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754;
+
/* Choosing multiple program flow means that we may get 2-vertex threads,
* which will have the channel mask for dwords 4-7 enabled in the thread,
* and those dwords will be written to the second URB handle when we
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index f221846f0c8..631f351699b 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -110,7 +110,15 @@ brw_upload_wm_unit(struct brw_context *brw)
(wm->wm9.grf_reg_count_2 << 1)) >> 6;
wm->thread1.depth_coef_urb_read_offset = 1;
- wm->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
+ /* Use ALT floating point mode for ARB fragment programs, because they
+ * require 0^0 == 1. Even though _CurrentFragmentProgram is used for
+ * rendering, CurrentFragmentProgram is used for this check to
+ * differentiate between the GLSL and non-GLSL cases.
+ */
+ if (ctx->Shader.CurrentFragmentProgram == NULL)
+ wm->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
+ else
+ wm->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754;
wm->thread1.binding_table_entry_count = 0;