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-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c8
-rw-r--r--src/mesa/drivers/dri/i965/gen7_misc_state.c8
-rw-r--r--src/mesa/drivers/dri/intel/intel_context.c4
-rw-r--r--src/mesa/drivers/dri/intel/intel_fbo.c52
-rw-r--r--src/mesa/drivers/dri/intel/intel_fbo.h6
-rw-r--r--src/mesa/drivers/dri/intel/intel_screen.c14
-rw-r--r--src/mesa/drivers/dri/intel/intel_span.c12
7 files changed, 55 insertions, 49 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 68e1e80d3b3..c364f4062cb 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -354,8 +354,8 @@ static void emit_depthbuffer(struct brw_context *brw)
(1 << 27) | /* tiled surface */
(BRW_SURFACE_2D << 29));
OUT_BATCH(0);
- OUT_BATCH(((stencil_irb->Base.Width - 1) << 6) |
- (stencil_irb->Base.Height - 1) << 19);
+ OUT_BATCH(((stencil_irb->Base.Base.Width - 1) << 6) |
+ (stencil_irb->Base.Base.Height - 1) << 19);
OUT_BATCH(0);
OUT_BATCH(0);
@@ -389,8 +389,8 @@ static void emit_depthbuffer(struct brw_context *brw)
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
offset);
OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
- (((depth_irb->Base.Width + tile_x)- 1) << 6) |
- (((depth_irb->Base.Height + tile_y) - 1) << 19));
+ (((depth_irb->Base.Base.Width + tile_x) - 1) << 6) |
+ (((depth_irb->Base.Base.Height + tile_y) - 1) << 19));
OUT_BATCH(0);
if (intel->is_g4x || intel->gen >= 5)
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index c2f58d53eef..d0ce54241b6 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -74,8 +74,8 @@ static void emit_depthbuffer(struct brw_context *brw)
/* 3DSTATE_STENCIL_BUFFER inherits surface type and dimensions. */
dw1 |= (BRW_SURFACE_2D << 29);
- dw3 = ((srb->Base.Width - 1) << 4) |
- ((srb->Base.Height - 1) << 18);
+ dw3 = ((srb->Base.Base.Width - 1) << 4) |
+ ((srb->Base.Base.Height - 1) << 18);
}
BEGIN_BATCH(7);
@@ -107,8 +107,8 @@ static void emit_depthbuffer(struct brw_context *brw)
OUT_RELOC(region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
offset);
- OUT_BATCH((((drb->Base.Width + tile_x) - 1) << 4) |
- (((drb->Base.Height + tile_y) - 1) << 18));
+ OUT_BATCH((((drb->Base.Base.Width + tile_x) - 1) << 4) |
+ (((drb->Base.Base.Height + tile_y) - 1) << 18));
OUT_BATCH(0);
OUT_BATCH(tile_x | (tile_y << 16));
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 30a01bb48f4..ffd953683e7 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -1401,8 +1401,8 @@ intel_verify_dri2_has_hiz(struct intel_context *intel,
/* 2. Create new depth/stencil renderbuffer. */
struct intel_renderbuffer *depth_stencil_rb =
intel_create_renderbuffer(MESA_FORMAT_S8_Z24);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depth_stencil_rb->Base);
- _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &depth_stencil_rb->Base);
+ _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depth_stencil_rb->Base.Base);
+ _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &depth_stencil_rb->Base.Base);
/* 3. Append DRI2BufferDepthStencil to attachment list. */
int old_count = *count;
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index 2e400e7d5c5..0bb61b5d642 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -132,11 +132,11 @@ intel_map_renderbuffer(struct gl_context *ctx,
void *map;
int stride;
- if (!irb && rb->Buffer) {
+ if (!irb && irb->Base.Buffer) {
/* this is a malloc'd renderbuffer (accum buffer) */
GLint bpp = _mesa_get_format_bytes(rb->Format);
- GLint rowStride = rb->RowStrideBytes;
- *out_map = (GLubyte *) rb->Buffer + y * rowStride + x * bpp;
+ GLint rowStride = irb->Base.RowStride;
+ *out_map = (GLubyte *) irb->Base.Buffer + y * rowStride + x * bpp;
*out_stride = rowStride;
return;
}
@@ -185,7 +185,7 @@ intel_unmap_renderbuffer(struct gl_context *ctx,
DBG("%s: rb %d (%s)\n", __FUNCTION__,
rb->Name, _mesa_get_format_name(rb->Format));
- if (!irb && rb->Buffer) {
+ if (!irb && irb->Base.Buffer) {
/* this is a malloc'd renderbuffer (accum buffer) */
/* nothing to do */
return;
@@ -368,9 +368,10 @@ intel_nop_alloc_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
struct intel_renderbuffer *
intel_create_renderbuffer(gl_format format)
{
- GET_CURRENT_CONTEXT(ctx);
-
struct intel_renderbuffer *irb;
+ struct gl_renderbuffer *rb;
+
+ GET_CURRENT_CONTEXT(ctx);
irb = CALLOC_STRUCT(intel_renderbuffer);
if (!irb) {
@@ -378,15 +379,17 @@ intel_create_renderbuffer(gl_format format)
return NULL;
}
- _mesa_init_renderbuffer(&irb->Base, 0);
- irb->Base.ClassID = INTEL_RB_CLASS;
- irb->Base._BaseFormat = _mesa_get_format_base_format(format);
- irb->Base.Format = format;
- irb->Base.InternalFormat = irb->Base._BaseFormat;
+ rb = &irb->Base.Base;
+
+ _mesa_init_renderbuffer(rb, 0);
+ rb->ClassID = INTEL_RB_CLASS;
+ rb->_BaseFormat = _mesa_get_format_base_format(format);
+ rb->Format = format;
+ rb->InternalFormat = rb->_BaseFormat;
/* intel-specific methods */
- irb->Base.Delete = intel_delete_renderbuffer;
- irb->Base.AllocStorage = intel_alloc_window_storage;
+ rb->Delete = intel_delete_renderbuffer;
+ rb->AllocStorage = intel_alloc_window_storage;
return irb;
}
@@ -400,6 +403,7 @@ intel_new_renderbuffer(struct gl_context * ctx, GLuint name)
{
/*struct intel_context *intel = intel_context(ctx); */
struct intel_renderbuffer *irb;
+ struct gl_renderbuffer *rb;
irb = CALLOC_STRUCT(intel_renderbuffer);
if (!irb) {
@@ -407,15 +411,17 @@ intel_new_renderbuffer(struct gl_context * ctx, GLuint name)
return NULL;
}
- _mesa_init_renderbuffer(&irb->Base, name);
- irb->Base.ClassID = INTEL_RB_CLASS;
+ rb = &irb->Base.Base;
+
+ _mesa_init_renderbuffer(rb, name);
+ rb->ClassID = INTEL_RB_CLASS;
/* intel-specific methods */
- irb->Base.Delete = intel_delete_renderbuffer;
- irb->Base.AllocStorage = intel_alloc_renderbuffer_storage;
+ rb->Delete = intel_delete_renderbuffer;
+ rb->AllocStorage = intel_alloc_renderbuffer_storage;
/* span routines set in alloc_storage function */
- return &irb->Base;
+ return rb;
}
@@ -479,7 +485,7 @@ intel_renderbuffer_update_wrapper(struct intel_context *intel,
gl_format format,
GLenum internal_format)
{
- struct gl_renderbuffer *rb = &irb->Base;
+ struct gl_renderbuffer *rb = &irb->Base.Base;
rb->Format = format;
rb->InternalFormat = internal_format;
@@ -487,8 +493,8 @@ intel_renderbuffer_update_wrapper(struct intel_context *intel,
rb->Width = mt->level[level].width;
rb->Height = mt->level[level].height;
- irb->Base.Delete = intel_delete_renderbuffer;
- irb->Base.AllocStorage = intel_nop_alloc_storage;
+ rb->Delete = intel_delete_renderbuffer;
+ rb->AllocStorage = intel_nop_alloc_storage;
intel_miptree_check_level_layer(mt, level, layer);
irb->mt_level = level;
@@ -661,7 +667,7 @@ intel_render_texture(struct gl_context * ctx,
if (irb) {
/* bind the wrapper to the attachment point */
- _mesa_reference_renderbuffer(&att->Renderbuffer, &irb->Base);
+ _mesa_reference_renderbuffer(&att->Renderbuffer, &irb->Base.Base);
}
else {
/* fallback to software rendering */
@@ -682,7 +688,7 @@ intel_render_texture(struct gl_context * ctx,
DBG("Begin render %s texture tex=%u w=%d h=%d refcount=%d\n",
_mesa_get_format_name(image->TexFormat),
att->Texture->Name, image->Width, image->Height,
- irb->Base.RefCount);
+ irb->Base.Base.RefCount);
intel_image->used_as_render_target = true;
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h
index 5a0d865739b..a2c1b1a28dc 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.h
+++ b/src/mesa/drivers/dri/intel/intel_fbo.h
@@ -43,7 +43,7 @@ struct intel_texture_image;
*/
struct intel_renderbuffer
{
- struct gl_renderbuffer Base;
+ struct swrast_renderbuffer Base;
struct intel_mipmap_tree *mt; /**< The renderbuffer storage. */
drm_intel_bo *map_bo;
@@ -84,7 +84,7 @@ static INLINE struct intel_renderbuffer *
intel_renderbuffer(struct gl_renderbuffer *rb)
{
struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
- if (irb && irb->Base.ClassID == INTEL_RB_CLASS) {
+ if (irb && irb->Base.Base.ClassID == INTEL_RB_CLASS) {
/*_mesa_warning(NULL, "Returning non-intel Rb\n");*/
return irb;
}
@@ -119,7 +119,7 @@ intel_get_renderbuffer(struct gl_framebuffer *fb, gl_buffer_index attIndex)
static INLINE gl_format
intel_rb_format(const struct intel_renderbuffer *rb)
{
- return rb->Base.Format;
+ return rb->Base.Base.Format;
}
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 3d5689ab79e..1c5083038ea 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -437,11 +437,11 @@ intelCreateBuffer(__DRIscreen * driScrnPriv,
/* setup the hardware-based renderbuffers */
rb = intel_create_renderbuffer(rgbFormat);
- _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &rb->Base);
+ _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &rb->Base.Base);
if (mesaVis->doubleBufferMode) {
rb = intel_create_renderbuffer(rgbFormat);
- _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &rb->Base);
+ _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &rb->Base.Base);
}
/*
@@ -460,17 +460,17 @@ intelCreateBuffer(__DRIscreen * driScrnPriv,
* enum intel_dri2_has_hiz).
*/
rb = intel_create_renderbuffer(MESA_FORMAT_X8_Z24);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base);
+ _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base);
rb = intel_create_renderbuffer(MESA_FORMAT_S8);
- _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &rb->Base);
+ _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &rb->Base.Base);
} else {
/*
* Use combined depth/stencil. Note that the renderbuffer is
* attached to two attachment points.
*/
rb = intel_create_renderbuffer(MESA_FORMAT_S8_Z24);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base);
- _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &rb->Base);
+ _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base);
+ _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &rb->Base.Base);
}
}
else if (mesaVis->depthBits == 16) {
@@ -478,7 +478,7 @@ intelCreateBuffer(__DRIscreen * driScrnPriv,
/* just 16-bit depth buffer, no hw stencil */
struct intel_renderbuffer *depthRb
= intel_create_renderbuffer(MESA_FORMAT_Z16);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
+ _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base.Base);
}
else {
assert(mesaVis->depthBits == 0);
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index 34bcd28f9a2..9b6540d488f 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -121,7 +121,7 @@ intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
if (!irb)
return;
- if (rb->Map) {
+ if (irb->Base.Map) {
/* Renderbuffer is already mapped. This usually happens when a single
* buffer is attached to the framebuffer's depth and stencil attachment
* points.
@@ -132,8 +132,8 @@ intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
ctx->Driver.MapRenderbuffer(ctx, rb, 0, 0, rb->Width, rb->Height,
GL_MAP_READ_BIT | GL_MAP_WRITE_BIT,
&map, &stride);
- rb->Map = map;
- rb->RowStrideBytes = stride;
+ irb->Base.Map = map;
+ irb->Base.RowStride = stride;
}
static void
@@ -146,7 +146,7 @@ intel_renderbuffer_unmap(struct intel_context *intel,
if (!irb)
return;
- if (!rb->Map) {
+ if (!irb->Base.Map) {
/* Renderbuffer is already unmapped. This usually happens when a single
* buffer is attached to the framebuffer's depth and stencil attachment
* points.
@@ -156,8 +156,8 @@ intel_renderbuffer_unmap(struct intel_context *intel,
ctx->Driver.UnmapRenderbuffer(ctx, rb);
- rb->Map = NULL;
- rb->RowStrideBytes = 0;
+ irb->Base.Map = NULL;
+ irb->Base.RowStride = 0;
}
static void
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-21 17:55:16 +0000