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-rw-r--r--src/mesa/drivers/dri/i965/Makefile.sources1
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp.cpp108
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp.h122
-rw-r--r--src/mesa/drivers/dri/i965/gen6_blorp.cpp146
-rw-r--r--src/mesa/drivers/dri/i965/gen6_blorp.h43
-rw-r--r--src/mesa/drivers/dri/i965/gen7_blorp.cpp87
-rw-r--r--src/mesa/drivers/dri/i965/gen7_blorp.h5
7 files changed, 335 insertions, 177 deletions
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources
index 2d2e85bfd3a..41ce34b2e9c 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -110,6 +110,7 @@ i965_C_FILES = \
gen7_wm_surface_state.c
i965_CXX_FILES = \
+ brw_blorp.cpp \
brw_cubemap_normalize.cpp \
brw_fs.cpp \
brw_fs_cfg.cpp \
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
new file mode 100644
index 00000000000..95f039f63db
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -0,0 +1,108 @@
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "intel_fbo.h"
+
+#include "brw_blorp.h"
+#include "brw_defines.h"
+#include "gen6_blorp.h"
+#include "gen7_blorp.h"
+
+brw_blorp_mip_info::brw_blorp_mip_info()
+ : mt(NULL),
+ level(0),
+ layer(0)
+{
+}
+
+void
+brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
+ unsigned int level, unsigned int layer)
+{
+ intel_miptree_check_level_layer(mt, level, layer);
+
+ this->mt = mt;
+ this->level = level;
+ this->layer = layer;
+}
+
+void
+brw_blorp_mip_info::get_draw_offsets(uint32_t *draw_x, uint32_t *draw_y) const
+{
+ /* Construct a dummy renderbuffer just to extract tile offsets. */
+ struct intel_renderbuffer rb;
+ rb.mt = mt;
+ rb.mt_level = level;
+ rb.mt_layer = layer;
+ intel_renderbuffer_set_draw_offset(&rb);
+ *draw_x = rb.draw_x;
+ *draw_y = rb.draw_y;
+}
+
+brw_blorp_params::brw_blorp_params()
+ : x0(0),
+ y0(0),
+ x1(0),
+ y1(0),
+ depth_format(0),
+ hiz_op(GEN6_HIZ_OP_NONE)
+{
+}
+
+void
+brw_blorp_params::exec(struct intel_context *intel) const
+{
+ switch (intel->gen) {
+ case 6:
+ gen6_blorp_exec(intel, this);
+ break;
+ case 7:
+ gen7_blorp_exec(intel, this);
+ break;
+ default:
+ /* BLORP is not supported before Gen6. */
+ assert(false);
+ break;
+ }
+}
+
+brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
+ unsigned int level,
+ unsigned int layer,
+ gen6_hiz_op op)
+{
+ assert(op != GEN6_HIZ_OP_DEPTH_CLEAR); /* Not implemented yet. */
+ this->hiz_op = op;
+
+ depth.set(mt, level, layer);
+ depth.get_miplevel_dims(&x1, &y1);
+
+ assert(mt->hiz_mt != NULL);
+
+ switch (mt->format) {
+ case MESA_FORMAT_Z16: depth_format = BRW_DEPTHFORMAT_D16_UNORM; break;
+ case MESA_FORMAT_Z32_FLOAT: depth_format = BRW_DEPTHFORMAT_D32_FLOAT; break;
+ case MESA_FORMAT_X8_Z24: depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; break;
+ default: assert(0); break;
+ }
+}
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
new file mode 100644
index 00000000000..d250db5eb1e
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <stdint.h>
+
+#include "intel_mipmap_tree.h"
+
+struct brw_context;
+
+
+/**
+ * For an overview of the HiZ operations, see the following sections of the
+ * Sandy Bridge PRM, Volume 1, Part2:
+ * - 7.5.3.1 Depth Buffer Clear
+ * - 7.5.3.2 Depth Buffer Resolve
+ * - 7.5.3.3 Hierarchical Depth Buffer Resolve
+ */
+enum gen6_hiz_op {
+ GEN6_HIZ_OP_DEPTH_CLEAR,
+ GEN6_HIZ_OP_DEPTH_RESOLVE,
+ GEN6_HIZ_OP_HIZ_RESOLVE,
+ GEN6_HIZ_OP_NONE,
+};
+
+class brw_blorp_mip_info
+{
+public:
+ brw_blorp_mip_info();
+
+ void set(struct intel_mipmap_tree *mt,
+ unsigned int level, unsigned int layer);
+ void get_draw_offsets(uint32_t *draw_x, uint32_t *draw_y) const;
+
+ void get_miplevel_dims(uint32_t *width, uint32_t *height) const
+ {
+ *width = mt->level[level].width;
+ *height = mt->level[level].height;
+ }
+
+ struct intel_mipmap_tree *mt;
+ unsigned int level;
+ unsigned int layer;
+};
+
+class brw_blorp_params
+{
+public:
+ brw_blorp_params();
+
+ void exec(struct intel_context *intel) const;
+
+ uint32_t x0;
+ uint32_t y0;
+ uint32_t x1;
+ uint32_t y1;
+ brw_blorp_mip_info depth;
+ uint32_t depth_format;
+ enum gen6_hiz_op hiz_op;
+};
+
+/**
+ * Parameters for a HiZ or depth resolve operation.
+ *
+ * For an overview of HiZ ops, see the following sections of the Sandy Bridge
+ * PRM, Volume 1, Part 2:
+ * - 7.5.3.1 Depth Buffer Clear
+ * - 7.5.3.2 Depth Buffer Resolve
+ * - 7.5.3.3 Hierarchical Depth Buffer Resolve
+ */
+class brw_hiz_op_params : public brw_blorp_params
+{
+public:
+ brw_hiz_op_params(struct intel_mipmap_tree *mt,
+ unsigned int level, unsigned int layer,
+ gen6_hiz_op op);
+};
+
+/**
+ * \name BLORP internals
+ * \{
+ *
+ * Used internally by gen6_blorp_exec() and gen7_blorp_exec().
+ */
+
+void
+gen6_blorp_init(struct brw_context *brw);
+
+void
+gen6_blorp_emit_batch_head(struct brw_context *brw,
+ const brw_blorp_params *params);
+
+void
+gen6_blorp_emit_vertices(struct brw_context *brw,
+ const brw_blorp_params *params);
+
+void
+gen6_blorp_emit_depth_stencil_state(struct brw_context *brw,
+ const brw_blorp_params *params,
+ uint32_t *out_offset);
+/** \} */
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 604d380e702..0b1620a7d3e 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -31,23 +31,23 @@
#include "brw_defines.h"
#include "brw_state.h"
+#include "brw_blorp.h"
#include "gen6_blorp.h"
/**
- * \name Constants for HiZ VBO
+ * \name Constants for BLORP VBO
* \{
- *
- * \see brw_context::hiz::vertex_bo
*/
-#define GEN6_HIZ_NUM_VERTICES 3
-#define GEN6_HIZ_NUM_VUE_ELEMS 8
-#define GEN6_HIZ_VBO_SIZE (GEN6_HIZ_NUM_VERTICES \
- * GEN6_HIZ_NUM_VUE_ELEMS \
- * sizeof(float))
+#define GEN6_BLORP_NUM_VERTICES 3
+#define GEN6_BLORP_NUM_VUE_ELEMS 8
+#define GEN6_BLORP_VBO_SIZE (GEN6_BLORP_NUM_VERTICES \
+ * GEN6_BLORP_NUM_VUE_ELEMS \
+ * sizeof(float))
/** \} */
void
-gen6_hiz_emit_batch_head(struct brw_context *brw)
+gen6_blorp_emit_batch_head(struct brw_context *brw,
+ const brw_blorp_params *params)
{
struct gl_context *ctx = &brw->intel.ctx;
struct intel_context *intel = &brw->intel;
@@ -129,10 +129,8 @@ gen6_hiz_emit_batch_head(struct brw_context *brw)
}
void
-gen6_hiz_emit_vertices(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- unsigned int level,
- unsigned int layer)
+gen6_blorp_emit_vertices(struct brw_context *brw,
+ const brw_blorp_params *params)
{
struct intel_context *intel = &brw->intel;
uint32_t vertex_offset;
@@ -167,20 +165,18 @@ gen6_hiz_emit_vertices(struct brw_context *brw,
* "Vertex URB Entry (VUE) Formats".
*/
{
- const int width = mt->level[level].width;
- const int height = mt->level[level].height;
float *vertex_data;
- const float vertices[GEN6_HIZ_VBO_SIZE] = {
- /* v0 */ 0, 0, 0, 0, 0, height, 0, 1,
- /* v1 */ 0, 0, 0, 0, width, height, 0, 1,
- /* v2 */ 0, 0, 0, 0, 0, 0, 0, 1,
+ const float vertices[GEN6_BLORP_VBO_SIZE] = {
+ /* v0 */ 0, 0, 0, 0, params->x0, params->y1, 0, 1,
+ /* v1 */ 0, 0, 0, 0, params->x1, params->y1, 0, 1,
+ /* v2 */ 0, 0, 0, 0, params->x0, params->y0, 0, 1,
};
vertex_data = (float *) brw_state_batch(brw, AUB_TRACE_NO_TYPE,
- GEN6_HIZ_VBO_SIZE, 32,
+ GEN6_BLORP_VBO_SIZE, 32,
&vertex_offset);
- memcpy(vertex_data, vertices, GEN6_HIZ_VBO_SIZE);
+ memcpy(vertex_data, vertices, GEN6_BLORP_VBO_SIZE);
}
/* 3DSTATE_VERTEX_BUFFERS */
@@ -189,7 +185,7 @@ gen6_hiz_emit_vertices(struct brw_context *brw,
const int batch_length = 1 + 4 * num_buffers;
uint32_t dw0 = GEN6_VB0_ACCESS_VERTEXDATA |
- (GEN6_HIZ_NUM_VUE_ELEMS * sizeof(float)) << BRW_VB0_PITCH_SHIFT;
+ (GEN6_BLORP_NUM_VUE_ELEMS * sizeof(float)) << BRW_VB0_PITCH_SHIFT;
if (intel->gen >= 7)
dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
@@ -202,7 +198,7 @@ gen6_hiz_emit_vertices(struct brw_context *brw,
vertex_offset);
/* end address */
OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
- vertex_offset + GEN6_HIZ_VBO_SIZE - 1);
+ vertex_offset + GEN6_BLORP_VBO_SIZE - 1);
OUT_BATCH(0);
ADVANCE_BATCH();
}
@@ -210,7 +206,7 @@ gen6_hiz_emit_vertices(struct brw_context *brw,
/* 3DSTATE_VERTEX_ELEMENTS
*
* Fetch dwords 0 - 7 from each VUE. See the comments above where
- * hiz->vertex_bo is filled with data.
+ * the vertex_bo is filled with data.
*/
{
const int num_elements = 2;
@@ -239,46 +235,24 @@ gen6_hiz_emit_vertices(struct brw_context *brw,
}
/**
- * \brief Execute a HiZ op on a miptree slice.
+ * \brief Execute a blit or render pass operation.
*
- * To execute the HiZ op, this function manually constructs and emits a batch
- * to "draw" the HiZ op's rectangle primitive. The batchbuffer is flushed
- * before constructing and after emitting the batch.
+ * To execute the operation, this function manually constructs and emits a
+ * batch to draw a rectangle primitive. The batchbuffer is flushed before
+ * constructing and after emitting the batch.
*
* This function alters no GL state.
- *
- * For an overview of HiZ ops, see the following sections of the Sandy Bridge
- * PRM, Volume 1, Part 2:
- * - 7.5.3.1 Depth Buffer Clear
- * - 7.5.3.2 Depth Buffer Resolve
- * - 7.5.3.3 Hierarchical Depth Buffer Resolve
*/
-static void
-gen6_hiz_exec(struct intel_context *intel,
- struct intel_mipmap_tree *mt,
- unsigned int level,
- unsigned int layer,
- enum gen6_hiz_op op)
+void
+gen6_blorp_exec(struct intel_context *intel,
+ const brw_blorp_params *params)
{
struct gl_context *ctx = &intel->ctx;
struct brw_context *brw = brw_context(ctx);
uint32_t draw_x, draw_y;
uint32_t tile_mask_x, tile_mask_y;
- assert(op != GEN6_HIZ_OP_DEPTH_CLEAR); /* Not implemented yet. */
- assert(mt->hiz_mt != NULL);
- intel_miptree_check_level_layer(mt, level, layer);
-
- {
- /* Construct a dummy renderbuffer just to extract tile offsets. */
- struct intel_renderbuffer rb;
- rb.mt = mt;
- rb.mt_level = level;
- rb.mt_layer = layer;
- intel_renderbuffer_set_draw_offset(&rb);
- draw_x = rb.draw_x;
- draw_y = rb.draw_y;
- }
+ params->depth.get_draw_offsets(&draw_x, &draw_y);
/* Compute masks to determine how much of draw_x and draw_y should be
* performed using the fine adjustment of "depth coordinate offset X/Y"
@@ -287,8 +261,9 @@ gen6_hiz_exec(struct intel_context *intel,
*/
{
uint32_t depth_mask_x, depth_mask_y, hiz_mask_x, hiz_mask_y;
- intel_region_get_tile_masks(mt->region, &depth_mask_x, &depth_mask_y);
- intel_region_get_tile_masks(mt->hiz_mt->region,
+ intel_region_get_tile_masks(params->depth.mt->region,
+ &depth_mask_x, &depth_mask_y);
+ intel_region_get_tile_masks(params->depth.mt->hiz_mt->region,
&hiz_mask_x, &hiz_mask_y);
/* Each HiZ row represents 2 rows of pixels */
@@ -298,8 +273,8 @@ gen6_hiz_exec(struct intel_context *intel,
tile_mask_y = depth_mask_y | hiz_mask_y;
}
- gen6_hiz_emit_batch_head(brw);
- gen6_hiz_emit_vertices(brw, mt, level, layer);
+ gen6_blorp_emit_batch_head(brw, params);
+ gen6_blorp_emit_vertices(brw, params);
/* 3DSTATE_URB
*
@@ -334,7 +309,7 @@ gen6_hiz_exec(struct intel_context *intel,
*/
{
uint32_t depthstencil_offset;
- gen6_hiz_emit_depth_stencil_state(brw, op, &depthstencil_offset);
+ gen6_blorp_emit_depth_stencil_state(brw, params, &depthstencil_offset);
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
@@ -388,7 +363,7 @@ gen6_hiz_exec(struct intel_context *intel,
*
* Disable the clipper.
*
- * The HiZ op emits a rectangle primitive, which requires clipping to
+ * The BLORP op emits a rectangle primitive, which requires clipping to
* be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1
* Section 1.3 "3D Primitives Overview":
* RECTLIST:
@@ -448,7 +423,7 @@ gen6_hiz_exec(struct intel_context *intel,
{
uint32_t dw4 = 0;
- switch (op) {
+ switch (params->hiz_op) {
case GEN6_HIZ_OP_DEPTH_CLEAR:
assert(!"not implemented");
dw4 |= GEN6_WM_DEPTH_CLEAR;
@@ -479,14 +454,15 @@ gen6_hiz_exec(struct intel_context *intel,
/* 3DSTATE_DEPTH_BUFFER */
{
- uint32_t width = mt->level[level].width;
- uint32_t height = mt->level[level].height;
+ uint32_t width, height;
+ params->depth.get_miplevel_dims(&width, &height);
uint32_t tile_x = draw_x & tile_mask_x;
uint32_t tile_y = draw_y & tile_mask_y;
- uint32_t offset = intel_region_get_aligned_offset(mt->region,
- draw_x & ~tile_mask_x,
- draw_y & ~tile_mask_y);
+ uint32_t offset =
+ intel_region_get_aligned_offset(params->depth.mt->region,
+ draw_x & ~tile_mask_x,
+ draw_y & ~tile_mask_y);
/* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
* (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
@@ -506,27 +482,21 @@ gen6_hiz_exec(struct intel_context *intel,
tile_x &= ~7;
tile_y &= ~7;
- uint32_t format;
- switch (mt->format) {
- case MESA_FORMAT_Z16: format = BRW_DEPTHFORMAT_D16_UNORM; break;
- case MESA_FORMAT_Z32_FLOAT: format = BRW_DEPTHFORMAT_D32_FLOAT; break;
- case MESA_FORMAT_X8_Z24: format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; break;
- default: assert(0); break;
- }
-
intel_emit_post_sync_nonzero_flush(intel);
intel_emit_depth_stall_flushes(intel);
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
- OUT_BATCH(((mt->region->pitch * mt->region->cpp) - 1) |
- format << 18 |
+ uint32_t pitch_bytes =
+ params->depth.mt->region->pitch * params->depth.mt->region->cpp;
+ OUT_BATCH((pitch_bytes - 1) |
+ params->depth_format << 18 |
1 << 21 | /* separate stencil enable */
1 << 22 | /* hiz enable */
BRW_TILEWALK_YMAJOR << 26 |
1 << 27 | /* y-tiled */
BRW_SURFACE_2D << 29);
- OUT_RELOC(mt->region->bo,
+ OUT_RELOC(params->depth.mt->region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
offset);
OUT_BATCH(BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1 |
@@ -541,7 +511,7 @@ gen6_hiz_exec(struct intel_context *intel,
/* 3DSTATE_HIER_DEPTH_BUFFER */
{
- struct intel_region *hiz_region = mt->hiz_mt->region;
+ struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
uint32_t hiz_offset =
intel_region_get_aligned_offset(hiz_region,
draw_x & ~tile_mask_x,
@@ -583,8 +553,8 @@ gen6_hiz_exec(struct intel_context *intel,
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
OUT_BATCH(0);
- OUT_BATCH(((mt->level[level].width - 1) & 0xffff) |
- ((mt->level[level].height - 1) << 16));
+ OUT_BATCH(((params->x1 - 1) & 0xffff) |
+ ((params->y1 - 1) << 16));
OUT_BATCH(0);
ADVANCE_BATCH();
}
@@ -604,7 +574,7 @@ gen6_hiz_exec(struct intel_context *intel,
}
/* See comments above at first invocation of intel_flush() in
- * gen6_hiz_emit_batch_head().
+ * gen6_blorp_emit_batch_head().
*/
intel_flush(ctx);
@@ -618,9 +588,9 @@ gen6_hiz_exec(struct intel_context *intel,
* CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
*/
void
-gen6_hiz_emit_depth_stencil_state(struct brw_context *brw,
- enum gen6_hiz_op op,
- uint32_t *out_offset)
+gen6_blorp_emit_depth_stencil_state(struct brw_context *brw,
+ const brw_blorp_params *params,
+ uint32_t *out_offset)
{
struct gen6_depth_stencil_state *state;
state = (struct gen6_depth_stencil_state *)
@@ -635,7 +605,7 @@ gen6_hiz_emit_depth_stencil_state(struct brw_context *brw,
* - 7.5.3.3 Hierarchical Depth Buffer Resolve
*/
state->ds2.depth_write_enable = 1;
- if (op == GEN6_HIZ_OP_DEPTH_RESOLVE) {
+ if (params->hiz_op == GEN6_HIZ_OP_DEPTH_RESOLVE) {
state->ds2.depth_test_enable = 1;
state->ds2.depth_test_func = COMPAREFUNC_NEVER;
}
@@ -648,7 +618,8 @@ gen6_resolve_hiz_slice(struct intel_context *intel,
uint32_t level,
uint32_t layer)
{
- gen6_hiz_exec(intel, mt, level, layer, GEN6_HIZ_OP_HIZ_RESOLVE);
+ brw_hiz_op_params params(mt, level, layer, GEN6_HIZ_OP_HIZ_RESOLVE);
+ gen6_blorp_exec(intel, &params);
}
/** \see intel_context::vtbl::resolve_depth_slice */
@@ -658,5 +629,6 @@ gen6_resolve_depth_slice(struct intel_context *intel,
uint32_t level,
uint32_t layer)
{
- gen6_hiz_exec(intel, mt, level, layer, GEN6_HIZ_OP_DEPTH_RESOLVE);
+ brw_hiz_op_params params(mt, level, layer, GEN6_HIZ_OP_DEPTH_RESOLVE);
+ gen6_blorp_exec(intel, &params);
}
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.h b/src/mesa/drivers/dri/i965/gen6_blorp.h
index 5d6eefc2d64..80961480362 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.h
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.h
@@ -32,44 +32,6 @@ extern "C" {
struct intel_context;
struct intel_mipmap_tree;
-/**
- * For an overview of the HiZ operations, see the following sections of the
- * Sandy Bridge PRM, Volume 1, Part2:
- * - 7.5.3.1 Depth Buffer Clear
- * - 7.5.3.2 Depth Buffer Resolve
- * - 7.5.3.3 Hierarchical Depth Buffer Resolve
- */
-enum gen6_hiz_op {
- GEN6_HIZ_OP_DEPTH_CLEAR,
- GEN6_HIZ_OP_DEPTH_RESOLVE,
- GEN6_HIZ_OP_HIZ_RESOLVE,
-};
-
-/**
- * \name HiZ internals
- * \{
- *
- * Used internally by gen6_hiz_exec() and gen7_hiz_exec().
- */
-
-void
-gen6_hiz_init(struct brw_context *brw);
-
-void
-gen6_hiz_emit_batch_head(struct brw_context *brw);
-
-void
-gen6_hiz_emit_vertices(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- unsigned int level,
- unsigned int layer);
-
-void
-gen6_hiz_emit_depth_stencil_state(struct brw_context *brw,
- enum gen6_hiz_op op,
- uint32_t *out_offset);
-/** \} */
-
void
gen6_resolve_hiz_slice(struct intel_context *intel,
struct intel_mipmap_tree *mt,
@@ -84,4 +46,9 @@ gen6_resolve_depth_slice(struct intel_context *intel,
#ifdef __cplusplus
}
+
+void
+gen6_blorp_exec(struct intel_context *intel,
+ const brw_blorp_params *params);
+
#endif
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 9d21ec97819..3172c4f988a 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -31,46 +31,22 @@
#include "brw_defines.h"
#include "brw_state.h"
-#include "gen6_blorp.h"
+#include "brw_blorp.h"
#include "gen7_blorp.h"
/**
- * \copydoc gen6_hiz_exec()
+ * \copydoc gen6_blorp_exec()
*/
-static void
-gen7_hiz_exec(struct intel_context *intel,
- struct intel_mipmap_tree *mt,
- unsigned int level,
- unsigned int layer,
- enum gen6_hiz_op op)
+void
+gen7_blorp_exec(struct intel_context *intel,
+ const brw_blorp_params *params)
{
struct gl_context *ctx = &intel->ctx;
struct brw_context *brw = brw_context(ctx);
uint32_t draw_x, draw_y;
uint32_t tile_mask_x, tile_mask_y;
- assert(op != GEN6_HIZ_OP_DEPTH_CLEAR); /* Not implemented yet. */
- assert(mt->hiz_mt != NULL);
- intel_miptree_check_level_layer(mt, level, layer);
-
- uint32_t depth_format;
- switch (mt->format) {
- case MESA_FORMAT_Z16: depth_format = BRW_DEPTHFORMAT_D16_UNORM; break;
- case MESA_FORMAT_Z32_FLOAT: depth_format = BRW_DEPTHFORMAT_D32_FLOAT; break;
- case MESA_FORMAT_X8_Z24: depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; break;
- default: assert(0); break;
- }
-
- {
- /* Construct a dummy renderbuffer just to extract tile offsets. */
- struct intel_renderbuffer rb;
- rb.mt = mt;
- rb.mt_level = level;
- rb.mt_layer = layer;
- intel_renderbuffer_set_draw_offset(&rb);
- draw_x = rb.draw_x;
- draw_y = rb.draw_y;
- }
+ params->depth.get_draw_offsets(&draw_x, &draw_y);
/* Compute masks to determine how much of draw_x and draw_y should be
* performed using the fine adjustment of "depth coordinate offset X/Y"
@@ -79,8 +55,9 @@ gen7_hiz_exec(struct intel_context *intel,
*/
{
uint32_t depth_mask_x, depth_mask_y, hiz_mask_x, hiz_mask_y;
- intel_region_get_tile_masks(mt->region, &depth_mask_x, &depth_mask_y);
- intel_region_get_tile_masks(mt->hiz_mt->region,
+ intel_region_get_tile_masks(params->depth.mt->region,
+ &depth_mask_x, &depth_mask_y);
+ intel_region_get_tile_masks(params->depth.mt->hiz_mt->region,
&hiz_mask_x, &hiz_mask_y);
/* Each HiZ row represents 2 rows of pixels */
@@ -90,8 +67,8 @@ gen7_hiz_exec(struct intel_context *intel,
tile_mask_y = depth_mask_y | hiz_mask_y;
}
- gen6_hiz_emit_batch_head(brw);
- gen6_hiz_emit_vertices(brw, mt, level, layer);
+ gen6_blorp_emit_batch_head(brw, params);
+ gen6_blorp_emit_vertices(brw, params);
/* 3DSTATE_URB_VS
* 3DSTATE_URB_HS
@@ -139,7 +116,7 @@ gen7_hiz_exec(struct intel_context *intel,
*/
{
uint32_t depthstencil_offset;
- gen6_hiz_emit_depth_stencil_state(brw, op, &depthstencil_offset);
+ gen6_blorp_emit_depth_stencil_state(brw, params, &depthstencil_offset);
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
@@ -238,7 +215,7 @@ gen7_hiz_exec(struct intel_context *intel,
*
* Disable the clipper.
*
- * The HiZ op emits a rectangle primitive, which requires clipping to
+ * The BLORP op emits a rectangle primitive, which requires clipping to
* be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1
* Section 1.3 "3D Primitives Overview":
* RECTLIST:
@@ -278,7 +255,8 @@ gen7_hiz_exec(struct intel_context *intel,
{
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
- OUT_BATCH(depth_format << GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
+ OUT_BATCH(params->depth_format <<
+ GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
@@ -306,7 +284,7 @@ gen7_hiz_exec(struct intel_context *intel,
{
uint32_t dw1 = 0;
- switch (op) {
+ switch (params->hiz_op) {
case GEN6_HIZ_OP_DEPTH_CLEAR:
assert(!"not implemented");
dw1 |= GEN7_WM_DEPTH_CLEAR;
@@ -355,14 +333,15 @@ gen7_hiz_exec(struct intel_context *intel,
/* 3DSTATE_DEPTH_BUFFER */
{
- uint32_t width = mt->level[level].width;
- uint32_t height = mt->level[level].height;
+ uint32_t width, height;
+ params->depth.get_miplevel_dims(&width, &height);
uint32_t tile_x = draw_x & tile_mask_x;
uint32_t tile_y = draw_y & tile_mask_y;
- uint32_t offset = intel_region_get_aligned_offset(mt->region,
- draw_x & ~tile_mask_x,
- draw_y & ~tile_mask_y);
+ uint32_t offset =
+ intel_region_get_aligned_offset(params->depth.mt->region,
+ draw_x & ~tile_mask_x,
+ draw_y & ~tile_mask_y);
/* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
* (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
@@ -386,12 +365,14 @@ gen7_hiz_exec(struct intel_context *intel,
BEGIN_BATCH(7);
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
- OUT_BATCH(((mt->region->pitch * mt->region->cpp) - 1) |
- depth_format << 18 |
+ uint32_t pitch_bytes =
+ params->depth.mt->region->pitch * params->depth.mt->region->cpp;
+ OUT_BATCH((pitch_bytes - 1) |
+ params->depth_format << 18 |
1 << 22 | /* hiz enable */
1 << 28 | /* depth write */
BRW_SURFACE_2D << 29);
- OUT_RELOC(mt->region->bo,
+ OUT_RELOC(params->depth.mt->region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
offset);
OUT_BATCH((width + tile_x - 1) << 4 |
@@ -405,7 +386,7 @@ gen7_hiz_exec(struct intel_context *intel,
/* 3DSTATE_HIER_DEPTH_BUFFER */
{
- struct intel_region *hiz_region = mt->hiz_mt->region;
+ struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
uint32_t hiz_offset =
intel_region_get_aligned_offset(hiz_region,
draw_x & ~tile_mask_x,
@@ -450,8 +431,8 @@ gen7_hiz_exec(struct intel_context *intel,
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
OUT_BATCH(0);
- OUT_BATCH(((mt->level[level].width - 1) & 0xffff) |
- ((mt->level[level].height - 1) << 16));
+ OUT_BATCH(((params->x1 - 1) & 0xffff) |
+ ((params->y1 - 1) << 16));
OUT_BATCH(0);
ADVANCE_BATCH();
}
@@ -471,7 +452,7 @@ gen7_hiz_exec(struct intel_context *intel,
}
/* See comments above at first invocation of intel_flush() in
- * gen6_hiz_emit_batch_head().
+ * gen6_blorp_emit_batch_head().
*/
intel_flush(ctx);
@@ -487,7 +468,8 @@ gen7_resolve_hiz_slice(struct intel_context *intel,
uint32_t level,
uint32_t layer)
{
- gen7_hiz_exec(intel, mt, level, layer, GEN6_HIZ_OP_HIZ_RESOLVE);
+ brw_hiz_op_params params(mt, level, layer, GEN6_HIZ_OP_HIZ_RESOLVE);
+ gen7_blorp_exec(intel, &params);
}
/** \copydoc gen6_resolve_depth_slice() */
@@ -497,5 +479,6 @@ gen7_resolve_depth_slice(struct intel_context *intel,
uint32_t level,
uint32_t layer)
{
- gen7_hiz_exec(intel, mt, level, layer, GEN6_HIZ_OP_DEPTH_RESOLVE);
+ brw_hiz_op_params params(mt, level, layer, GEN6_HIZ_OP_DEPTH_RESOLVE);
+ gen7_blorp_exec(intel, &params);
}
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.h b/src/mesa/drivers/dri/i965/gen7_blorp.h
index 6c0fc84eca1..43e4a10faea 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.h
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.h
@@ -48,4 +48,9 @@ gen7_resolve_depth_slice(struct intel_context *intel,
#ifdef __cplusplus
}
+
+void
+gen7_blorp_exec(struct intel_context *intel,
+ const brw_blorp_params *params);
+
#endif
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 16:35:30 +0000