diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/freedreno/a5xx/a5xx.xml.h | 22 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/a5xx/fd5_emit.c | 7 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/a5xx/fd5_zsa.c | 6 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/a5xx/fd5_zsa.h | 1 |
4 files changed, 27 insertions, 9 deletions
diff --git a/src/gallium/drivers/freedreno/a5xx/a5xx.xml.h b/src/gallium/drivers/freedreno/a5xx/a5xx.xml.h index 1e897530743..73e50868f73 100644 --- a/src/gallium/drivers/freedreno/a5xx/a5xx.xml.h +++ b/src/gallium/drivers/freedreno/a5xx/a5xx.xml.h @@ -8,7 +8,7 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/ilia/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 141659 bytes, from 2017-07-04 21:50:01) +- /home/ilia/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 141764 bytes, from 2017-07-05 00:40:13) - /home/ilia/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-11 01:04:14) - /home/ilia/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-07-04 02:59:47) - /home/ilia/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-07-04 02:59:47) @@ -3419,7 +3419,25 @@ static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) return ((val) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; } -#define REG_A5XX_UNKNOWN_E1C7 0x0000e1c7 +#define REG_A5XX_RB_STENCILREFMASK_BF 0x0000e1c7 +#define A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff +#define A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 +static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) +{ + return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; +} +#define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 +#define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 +static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) +{ + return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; +} +#define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 +#define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 +static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) +{ + return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; +} #define REG_A5XX_RB_WINDOW_OFFSET 0x0000e1d0 #define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c index a4f475a9b5b..bede05e9812 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c +++ b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c @@ -522,9 +522,11 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring, struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa); struct pipe_stencil_ref *sr = &ctx->stencil_ref; - OUT_PKT4(ring, REG_A5XX_RB_STENCILREFMASK, 1); + OUT_PKT4(ring, REG_A5XX_RB_STENCILREFMASK, 2); OUT_RING(ring, zsa->rb_stencilrefmask | A5XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0])); + OUT_RING(ring, zsa->rb_stencilrefmask_bf | + A5XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1])); } if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) { @@ -922,9 +924,6 @@ t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) OUT_PKT4(ring, REG_A5XX_UNKNOWN_E093, 1); OUT_RING(ring, 0x00000000); /* UNKNOWN_E093 */ - OUT_PKT4(ring, REG_A5XX_UNKNOWN_E1C7, 1); - OUT_RING(ring, 0x00000000); /* UNKNOWN_E1C7 */ - OUT_PKT4(ring, REG_A5XX_UNKNOWN_E29A, 1); OUT_RING(ring, 0x00ffff00); /* UNKNOWN_E29A */ diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_zsa.c b/src/gallium/drivers/freedreno/a5xx/fd5_zsa.c index ee8e0fce375..495a4cc8a3f 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_zsa.c +++ b/src/gallium/drivers/freedreno/a5xx/fd5_zsa.c @@ -99,9 +99,9 @@ fd5_zsa_state_create(struct pipe_context *pctx, A5XX_RB_STENCIL_CONTROL_FAIL_BF(fd_stencil_op(bs->fail_op)) | A5XX_RB_STENCIL_CONTROL_ZPASS_BF(fd_stencil_op(bs->zpass_op)) | A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(fd_stencil_op(bs->zfail_op)); -// so->rb_stencilrefmask_bf |= -// A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(bs->writemask) | -// A5XX_RB_STENCILREFMASK_BF_STENCILMASK(bs->valuemask); + so->rb_stencilrefmask_bf |= + A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(bs->writemask) | + A5XX_RB_STENCILREFMASK_BF_STENCILMASK(bs->valuemask); } } diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_zsa.h b/src/gallium/drivers/freedreno/a5xx/fd5_zsa.h index cacc6323807..c15ba1aa8dc 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_zsa.h +++ b/src/gallium/drivers/freedreno/a5xx/fd5_zsa.h @@ -40,6 +40,7 @@ struct fd5_zsa_stateobj { uint32_t rb_depth_cntl; uint32_t rb_stencil_control; uint32_t rb_stencilrefmask; + uint32_t rb_stencilrefmask_bf; uint32_t gras_lrz_cntl; bool lrz_write; }; |