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-rw-r--r--src/mesa/pipe/cell/spu/spu_main.c30
-rw-r--r--src/mesa/pipe/cell/spu/spu_main.h4
-rw-r--r--src/mesa/pipe/cell/spu/spu_tile.c22
-rw-r--r--src/mesa/pipe/cell/spu/spu_tile.h6
4 files changed, 31 insertions, 31 deletions
diff --git a/src/mesa/pipe/cell/spu/spu_main.c b/src/mesa/pipe/cell/spu/spu_main.c
index 7446cc3eff6..0aee2aa6f90 100644
--- a/src/mesa/pipe/cell/spu/spu_main.c
+++ b/src/mesa/pipe/cell/spu/spu_main.c
@@ -83,13 +83,13 @@ really_clear_tiles(uint surfaceIndex)
if (surfaceIndex == 0) {
for (i = 0; i < TILE_SIZE; i++)
for (j = 0; j < TILE_SIZE; j++)
- ctile[i][j] = spu.fb.color_clear_value;
+ ctile[i][j] = spu.fb.color_clear_value; /*0xff00ff;*/
for (i = spu.init.id; i < num_tiles; i += spu.init.num_spus) {
uint tx = i % spu.fb.width_tiles;
uint ty = i / spu.fb.width_tiles;
if (tile_status[ty][tx] == TILE_STATUS_CLEAR) {
- put_tile(&spu.fb, tx, ty, (uint *) ctile, TAG_SURFACE_CLEAR, 0);
+ put_tile(tx, ty, (uint *) ctile, TAG_SURFACE_CLEAR, 0);
}
}
}
@@ -102,11 +102,11 @@ really_clear_tiles(uint surfaceIndex)
uint tx = i % spu.fb.width_tiles;
uint ty = i / spu.fb.width_tiles;
if (tile_status_z[ty][tx] == TILE_STATUS_CLEAR)
- put_tile(&spu.fb, tx, ty, (uint *) ctile, TAG_SURFACE_CLEAR, 1);
+ put_tile(tx, ty, (uint *) ctile, TAG_SURFACE_CLEAR, 1);
}
}
-#if 0
+#if 01
wait_on_mask(1 << TAG_SURFACE_CLEAR);
#endif
}
@@ -156,9 +156,9 @@ cmd_clear_surface(const struct cell_command_clear_surface *clear)
uint tx = i % spu.fb.width_tiles;
uint ty = i / spu.fb.width_tiles;
if (clear->surface == 0)
- put_tile(&spu.fb, tx, ty, (uint *) ctile, TAG_SURFACE_CLEAR, 0);
+ put_tile(tx, ty, (uint *) ctile, TAG_SURFACE_CLEAR, 0);
else
- put_tile(&spu.fb, tx, ty, (uint *) ztile, TAG_SURFACE_CLEAR, 1);
+ put_tile(tx, ty, (uint *) ztile, TAG_SURFACE_CLEAR, 1);
/* XXX we don't want this here, but it fixes bad tile results */
}
@@ -216,13 +216,15 @@ cmd_render(const struct cell_command_render *render)
uint i, j, vertex_size, vertex_bytes, index_bytes;
- if (Debug)
+ if (Debug) {
printf("SPU %u: RENDER prim %u, indices: %u, nr_vert: %u\n",
spu.init.id,
render->prim_type,
render->num_verts,
render->num_indexes);
-
+ printf(" bound: %g, %g .. %g, %g\n",
+ render->xmin, render->ymin, render->xmax, render->ymax);
+ }
ASSERT_ALIGN16(render->vertex_data);
ASSERT_ALIGN16(render->index_data);
@@ -289,12 +291,12 @@ cmd_render(const struct cell_command_render *render)
*/
if (spu.fb.depth_format == PIPE_FORMAT_Z16_UNORM) {
if (tile_status_z[ty][tx] != TILE_STATUS_CLEAR) {
- get_tile(&spu.fb, tx, ty, (uint *) ztile, TAG_READ_TILE_Z, 1);
+ get_tile(tx, ty, (uint *) ztile, TAG_READ_TILE_Z, 1);
}
}
if (tile_status[ty][tx] != TILE_STATUS_CLEAR) {
- get_tile(&spu.fb, tx, ty, (uint *) ctile, TAG_READ_TILE_COLOR, 0);
+ get_tile(tx, ty, (uint *) ctile, TAG_READ_TILE_COLOR, 0);
}
ASSERT(render->prim_type == PIPE_PRIM_TRIANGLES);
@@ -312,12 +314,12 @@ cmd_render(const struct cell_command_render *render)
/* write color/z tiles back to main framebuffer, if dirtied */
if (tile_status[ty][tx] == TILE_STATUS_DIRTY) {
- put_tile(&spu.fb, tx, ty, (uint *) ctile, TAG_WRITE_TILE_COLOR, 0);
+ put_tile(tx, ty, (uint *) ctile, TAG_WRITE_TILE_COLOR, 0);
tile_status[ty][tx] = TILE_STATUS_DEFINED;
}
if (spu.fb.depth_format == PIPE_FORMAT_Z16_UNORM) {
if (tile_status_z[ty][tx] == TILE_STATUS_DIRTY) {
- put_tile(&spu.fb, tx, ty, (uint *) ztile, TAG_WRITE_TILE_Z, 1);
+ put_tile(tx, ty, (uint *) ztile, TAG_WRITE_TILE_Z, 1);
tile_status_z[ty][tx] = TILE_STATUS_DEFINED;
}
}
@@ -361,7 +363,9 @@ cmd_state_depth_stencil(const struct pipe_depth_stencil_alpha_state *state)
printf("SPU %u: DEPTH_STENCIL: ztest %d\n",
spu.init.id,
state->depth.enabled);
- /* XXX copy/save the state */
+ /*
+ memcpy(&spu.depth_stencil, state, sizeof(*state));
+ */
}
diff --git a/src/mesa/pipe/cell/spu/spu_main.h b/src/mesa/pipe/cell/spu/spu_main.h
index ea43224d028..75fb5b388b0 100644
--- a/src/mesa/pipe/cell/spu/spu_main.h
+++ b/src/mesa/pipe/cell/spu/spu_main.h
@@ -33,7 +33,7 @@
#include "pipe/p_state.h"
-struct framebuffer {
+struct spu_framebuffer {
void *color_start; /**< addr of color surface in main memory */
void *depth_start; /**< addr of depth surface in main memory */
enum pipe_format color_format;
@@ -53,7 +53,7 @@ struct spu_global
{
struct cell_init_info init;
- struct framebuffer fb;
+ struct spu_framebuffer fb;
struct pipe_depth_stencil_alpha_state depth_stencil;
struct pipe_blend_state blend;
/* XXX more state to come */
diff --git a/src/mesa/pipe/cell/spu/spu_tile.c b/src/mesa/pipe/cell/spu/spu_tile.c
index 8fd9ab2905b..99d779007ea 100644
--- a/src/mesa/pipe/cell/spu/spu_tile.c
+++ b/src/mesa/pipe/cell/spu/spu_tile.c
@@ -40,17 +40,16 @@ ubyte tile_status_z[MAX_HEIGHT/TILE_SIZE][MAX_WIDTH/TILE_SIZE] ALIGN16_ATTRIB;
void
-get_tile(const struct framebuffer *fb, uint tx, uint ty, uint *tile,
- int tag, int zBuf)
+get_tile(uint tx, uint ty, uint *tile, int tag, int zBuf)
{
- const uint offset = ty * fb->width_tiles + tx;
+ const uint offset = ty * spu.fb.width_tiles + tx;
const uint bytesPerTile = TILE_SIZE * TILE_SIZE * (zBuf ? 2 : 4);
- const ubyte *src = zBuf ? fb->depth_start : fb->color_start;
+ const ubyte *src = zBuf ? spu.fb.depth_start : spu.fb.color_start;
src += offset * bytesPerTile;
- ASSERT(tx < fb->width_tiles);
- ASSERT(ty < fb->height_tiles);
+ ASSERT(tx < spu.fb.width_tiles);
+ ASSERT(ty < spu.fb.height_tiles);
ASSERT_ALIGN16(tile);
/*
printf("get_tile: dest: %p src: 0x%x size: %d\n",
@@ -66,17 +65,16 @@ get_tile(const struct framebuffer *fb, uint tx, uint ty, uint *tile,
void
-put_tile(const struct framebuffer *fb, uint tx, uint ty, const uint *tile,
- int tag, int zBuf)
+put_tile(uint tx, uint ty, const uint *tile, int tag, int zBuf)
{
- const uint offset = ty * fb->width_tiles + tx;
+ const uint offset = ty * spu.fb.width_tiles + tx;
const uint bytesPerTile = TILE_SIZE * TILE_SIZE * (zBuf ? 2 : 4);
- ubyte *dst = zBuf ? fb->depth_start : fb->color_start;
+ ubyte *dst = zBuf ? spu.fb.depth_start : spu.fb.color_start;
dst += offset * bytesPerTile;
- ASSERT(tx < fb->width_tiles);
- ASSERT(ty < fb->height_tiles);
+ ASSERT(tx < spu.fb.width_tiles);
+ ASSERT(ty < spu.fb.height_tiles);
ASSERT_ALIGN16(tile);
/*
printf("put_tile: src: %p dst: 0x%x size: %d\n",
diff --git a/src/mesa/pipe/cell/spu/spu_tile.h b/src/mesa/pipe/cell/spu/spu_tile.h
index 2ad469b5847..637923764b9 100644
--- a/src/mesa/pipe/cell/spu/spu_tile.h
+++ b/src/mesa/pipe/cell/spu/spu_tile.h
@@ -52,12 +52,10 @@ extern ubyte tile_status_z[MAX_HEIGHT/TILE_SIZE][MAX_WIDTH/TILE_SIZE] ALIGN16_AT
void
-get_tile(const struct framebuffer *fb, uint tx, uint ty, uint *tile,
- int tag, int zBuf);
+get_tile(uint tx, uint ty, uint *tile, int tag, int zBuf);
void
-put_tile(const struct framebuffer *fb, uint tx, uint ty, const uint *tile,
- int tag, int zBuf);
+put_tile(uint tx, uint ty, const uint *tile, int tag, int zBuf);
void
clear_tile(uint tile[TILE_SIZE][TILE_SIZE], uint value);
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-29 12:21:47 +0000