summaryrefslogtreecommitdiffstats
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/amd/addrlib/r800/ciaddrlib.cpp30
-rw-r--r--src/amd/addrlib/r800/ciaddrlib.h2
-rw-r--r--src/amd/addrlib/r800/egbaddrlib.cpp56
-rw-r--r--src/amd/addrlib/r800/egbaddrlib.h7
4 files changed, 41 insertions, 54 deletions
diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp
index 1024ff24549..5e5110a7016 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -1614,36 +1614,6 @@ VOID CiAddrLib::HwlComputeTileDataWidthAndHeightLinear(
/**
***************************************************************************************************
-* CiAddrLib::HwlStereoCheckRightOffsetPadding
-*
-* @brief
-* check if the height needs extra padding for stereo right eye offset, to avoid swizzling
-*
-* @return
-* TRUE is the extra padding is needed
-*
-* @note
-* Kalindi (Kabini) is the only one that needs this padding as there is a uncertain
-* possible HW issue where the right eye displays incorrectly with some type of swizzles, if
-* the right eye offset is not 64KB aligned - EPR#366461
-* Other Kaveri APUs also need the padding according to DXX team's report otherwise
-* corruption observed. - EPR#374788
-***************************************************************************************************
-*/
-BOOL_32 CiAddrLib::HwlStereoCheckRightOffsetPadding() const
-{
- BOOL_32 bNeedPadding = FALSE;
-
- if (m_settings.isKaveri)
- {
- bNeedPadding = TRUE;
- }
-
- return bNeedPadding;
-}
-
-/**
-***************************************************************************************************
* CiAddrLib::HwlComputeMetadataNibbleAddress
*
* @brief
diff --git a/src/amd/addrlib/r800/ciaddrlib.h b/src/amd/addrlib/r800/ciaddrlib.h
index 05e9eda2dbb..4862babb483 100644
--- a/src/amd/addrlib/r800/ciaddrlib.h
+++ b/src/amd/addrlib/r800/ciaddrlib.h
@@ -146,8 +146,6 @@ protected:
AddrTileMode* pTileMode,
AddrTileType* pTileType) const;
- virtual BOOL_32 HwlStereoCheckRightOffsetPadding() const;
-
virtual ADDR_E_RETURNCODE HwlComputeDccInfo(
const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
ADDR_COMPUTE_DCCINFO_OUTPUT* pOut) const;
diff --git a/src/amd/addrlib/r800/egbaddrlib.cpp b/src/amd/addrlib/r800/egbaddrlib.cpp
index 5d80906aea3..2085dc57cb0 100644
--- a/src/amd/addrlib/r800/egbaddrlib.cpp
+++ b/src/amd/addrlib/r800/egbaddrlib.cpp
@@ -525,24 +525,14 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceInfoMacroTiled(
&expNumSlices, microTileThickness);
if (pIn->flags.qbStereo &&
- (pOut->pStereoInfo != NULL) &&
- HwlStereoCheckRightOffsetPadding())
+ (pOut->pStereoInfo != NULL))
{
- // Eye height's bank bits are different from y == 0?
- // Since 3D rendering treats right eye buffer starting from y == "eye height" while
- // display engine treats it to be 0, so the bank bits may be different, we pad
- // more in height to make sure y == "eye height" has the same bank bits as y == 0.
- UINT_32 checkMask = pOut->pTileInfo->banks - 1;
- UINT_32 bankBits = 0;
- do
- {
- bankBits = (paddedHeight / 8 / pOut->pTileInfo->bankHeight) & checkMask;
+ UINT_32 stereoHeightAlign = HwlStereoCheckRightOffsetPadding(pOut->pTileInfo);
- if (bankBits)
- {
- paddedHeight += pOut->heightAlign;
- }
- } while (bankBits);
+ if (stereoHeightAlign != 0)
+ {
+ paddedHeight = PowTwoAlign(paddedHeight, stereoHeightAlign);
+ }
}
//
@@ -4591,3 +4581,37 @@ UINT_64 EgBasedAddrLib::HwlGetSizeAdjustmentMicroTiled(
return logicalSliceSize;
}
+/**
+***************************************************************************************************
+* EgBasedAddrLib::HwlStereoCheckRightOffsetPadding
+*
+* @brief
+* check if the height needs extra padding for stereo right eye offset, to avoid swizzling
+*
+* @return
+* TRUE is the extra padding is needed
+*
+***************************************************************************************************
+*/
+UINT_32 EgBasedAddrLib::HwlStereoCheckRightOffsetPadding(
+ ADDR_TILEINFO* pTileInfo ///< Tiling info
+ ) const
+{
+ UINT_32 stereoHeightAlign = 0;
+
+ if (pTileInfo->macroAspectRatio > 2)
+ {
+ // Since 3D rendering treats right eye surface starting from y == "eye height" while
+ // display engine treats it to be 0, so the bank bits may be different.
+ // Additional padding in height is required to make sure it's possible
+ // to achieve synonym by adjusting bank swizzle of right eye surface.
+
+ static const UINT_32 StereoAspectRatio = 2;
+ stereoHeightAlign = pTileInfo->banks *
+ pTileInfo->bankHeight *
+ MicroTileHeight /
+ StereoAspectRatio;
+ }
+
+ return stereoHeightAlign;
+}
diff --git a/src/amd/addrlib/r800/egbaddrlib.h b/src/amd/addrlib/r800/egbaddrlib.h
index 25e38964be0..ca1d07d062f 100644
--- a/src/amd/addrlib/r800/egbaddrlib.h
+++ b/src/amd/addrlib/r800/egbaddrlib.h
@@ -224,12 +224,7 @@ protected:
{
}
- /// Virtual function to check if the height needs extra padding
- /// for stereo right eye offset, to avoid bank pipe swizzle
- virtual BOOL_32 HwlStereoCheckRightOffsetPadding() const
- {
- return FALSE;
- }
+ virtual UINT_32 HwlStereoCheckRightOffsetPadding(ADDR_TILEINFO* pTileInfo) const;
virtual BOOL_32 HwlReduceBankWidthHeight(
UINT_32 tileSize, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples,