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-rw-r--r--src/mesa/drivers/dri/i965/brw_compute.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_draw.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_draw_upload.c5
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_surface_state.c16
-rw-r--r--src/mesa/drivers/dri/i965/genX_state_upload.c2
-rw-r--r--src/mesa/drivers/dri/i965/intel_buffer_objects.c6
-rw-r--r--src/mesa/drivers/dri/i965/intel_buffer_objects.h7
-rw-r--r--src/mesa/drivers/dri/i965/intel_pixel_draw.c2
-rw-r--r--src/mesa/drivers/dri/i965/intel_tex.c3
9 files changed, 26 insertions, 19 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_compute.c b/src/mesa/drivers/dri/i965/brw_compute.c
index 2867a142f13..d6cb0161f40 100644
--- a/src/mesa/drivers/dri/i965/brw_compute.c
+++ b/src/mesa/drivers/dri/i965/brw_compute.c
@@ -263,7 +263,7 @@ brw_dispatch_compute_indirect(struct gl_context *ctx, GLintptr indirect)
struct brw_bo *bo =
intel_bufferobj_buffer(brw,
intel_buffer_object(indirect_buffer),
- indirect, 3 * sizeof(GLuint));
+ indirect, 3 * sizeof(GLuint), false);
brw->compute.num_work_groups_bo = bo;
brw->compute.num_work_groups_offset = indirect;
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 2ac35032c94..182a140339b 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -222,7 +222,7 @@ brw_emit_prim(struct brw_context *brw,
struct gl_buffer_object *indirect_buffer = brw->ctx.DrawIndirectBuffer;
struct brw_bo *bo = intel_bufferobj_buffer(brw,
intel_buffer_object(indirect_buffer),
- prim->indirect_offset, 5 * sizeof(GLuint));
+ prim->indirect_offset, 5 * sizeof(GLuint), false);
indirect_flag = GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE;
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index baa1de353b4..5b56aaf1862 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -622,7 +622,8 @@ brw_prepare_vertices(struct brw_context *brw)
const uint32_t start = buffer_range_start[i];
const uint32_t range = buffer_range_end[i] - buffer_range_start[i];
- buffer->bo = intel_bufferobj_buffer(brw, enabled_buffer[i], start, range);
+ buffer->bo = intel_bufferobj_buffer(brw, enabled_buffer[i], start,
+ range, false);
brw_bo_reference(buffer->bo);
}
@@ -739,7 +740,7 @@ brw_upload_indices(struct brw_context *brw)
struct brw_bo *bo =
intel_bufferobj_buffer(brw, intel_buffer_object(bufferobj),
- offset, ib_size);
+ offset, ib_size, false);
if (bo != brw->ib.bo) {
brw_bo_unreference(brw->ib.bo);
brw->ib.bo = bo;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 3615c1805ec..d4960a01cbd 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -698,7 +698,8 @@ brw_update_buffer_texture_surface(struct gl_context *ctx,
if (intel_obj) {
size = MIN2(size, intel_obj->Base.Size);
- bo = intel_bufferobj_buffer(brw, intel_obj, tObj->BufferOffset, size);
+ bo = intel_bufferobj_buffer(brw, intel_obj, tObj->BufferOffset, size,
+ false);
}
/* The ARB_texture_buffer_specification says:
@@ -786,7 +787,8 @@ brw_update_sol_surface(struct brw_context *brw,
uint32_t offset_bytes = 4 * offset_dwords;
struct brw_bo *bo = intel_bufferobj_buffer(brw, intel_bo,
offset_bytes,
- buffer_obj->Size - offset_bytes);
+ buffer_obj->Size - offset_bytes,
+ true);
uint32_t *surf = brw_state_batch(brw, 6 * 4, 32, out_offset);
uint32_t pitch_minus_1 = 4*stride_dwords - 1;
size_t size_dwords = buffer_obj->Size / 4;
@@ -1412,7 +1414,7 @@ brw_upload_ubo_surfaces(struct brw_context *brw, struct gl_program *prog,
struct brw_bo *bo =
intel_bufferobj_buffer(brw, intel_bo,
binding->Offset,
- size);
+ size, false);
brw_create_constant_surface(brw, bo, binding->Offset,
size,
&ubo_surf_offsets[i]);
@@ -1437,7 +1439,7 @@ brw_upload_ubo_surfaces(struct brw_context *brw, struct gl_program *prog,
struct brw_bo *bo =
intel_bufferobj_buffer(brw, intel_bo,
binding->Offset,
- size);
+ size, true);
brw_create_buffer_surface(brw, bo, binding->Offset,
size,
&ssbo_surf_offsets[i]);
@@ -1509,8 +1511,10 @@ brw_upload_abo_surfaces(struct brw_context *brw,
&ctx->AtomicBufferBindings[prog->sh.AtomicBuffers[i]->Binding];
struct intel_buffer_object *intel_bo =
intel_buffer_object(binding->BufferObject);
- struct brw_bo *bo = intel_bufferobj_buffer(
- brw, intel_bo, binding->Offset, intel_bo->Base.Size - binding->Offset);
+ struct brw_bo *bo =
+ intel_bufferobj_buffer(brw, intel_bo, binding->Offset,
+ intel_bo->Base.Size - binding->Offset,
+ true);
brw_emit_buffer_surface_state(brw, &surf_offsets[i], bo,
binding->Offset, ISL_FORMAT_RAW,
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c
index baa296192b3..b6678ec6941 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -3387,7 +3387,7 @@ genX(upload_3dstate_so_buffers)(struct brw_context *brw)
assert(start % 4 == 0);
uint32_t end = ALIGN(start + xfb_obj->Size[i], 4);
struct brw_bo *bo =
- intel_bufferobj_buffer(brw, bufferobj, start, end - start);
+ intel_bufferobj_buffer(brw, bufferobj, start, end - start, true);
assert(end <= bo->size);
brw_batch_emit(brw, GENX(3DSTATE_SO_BUFFER), sob) {
diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index fde6b224cd4..c1ee16c9f68 100644
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
@@ -540,7 +540,7 @@ brw_unmap_buffer(struct gl_context *ctx,
struct brw_bo *
intel_bufferobj_buffer(struct brw_context *brw,
struct intel_buffer_object *intel_obj,
- uint32_t offset, uint32_t size)
+ uint32_t offset, uint32_t size, bool write)
{
/* This is needed so that things like transform feedback and texture buffer
* objects that need a BO but don't want to check that they exist for
@@ -576,8 +576,8 @@ brw_copy_buffer_subdata(struct gl_context *ctx,
if (size == 0)
return;
- dst_bo = intel_bufferobj_buffer(brw, intel_dst, write_offset, size);
- src_bo = intel_bufferobj_buffer(brw, intel_src, read_offset, size);
+ dst_bo = intel_bufferobj_buffer(brw, intel_dst, write_offset, size, true);
+ src_bo = intel_bufferobj_buffer(brw, intel_src, read_offset, size, false);
intel_emit_linear_blit(brw,
dst_bo, write_offset,
diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.h b/src/mesa/drivers/dri/i965/intel_buffer_objects.h
index a1bfaa9ebc4..6058d824fee 100644
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.h
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.h
@@ -83,9 +83,10 @@ struct intel_buffer_object
/* Get the bm buffer associated with a GL bufferobject:
*/
struct brw_bo *intel_bufferobj_buffer(struct brw_context *brw,
- struct intel_buffer_object *obj,
- uint32_t offset,
- uint32_t size);
+ struct intel_buffer_object *obj,
+ uint32_t offset,
+ uint32_t size,
+ bool write);
void intel_upload_data(struct brw_context *brw,
const void *data,
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_draw.c b/src/mesa/drivers/dri/i965/intel_pixel_draw.c
index e84e4739df4..519e0596724 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_draw.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_draw.c
@@ -109,7 +109,7 @@ do_blit_drawpixels(struct gl_context * ctx,
format, type, 0, 0, 0);
src_buffer = intel_bufferobj_buffer(brw, src, src_offset,
- height * src_stride);
+ height * src_stride, false);
struct intel_mipmap_tree *pbo_mt =
intel_miptree_create_for_bo(brw,
diff --git a/src/mesa/drivers/dri/i965/intel_tex.c b/src/mesa/drivers/dri/i965/intel_tex.c
index 1751f109f77..f6cdb017c7b 100644
--- a/src/mesa/drivers/dri/i965/intel_tex.c
+++ b/src/mesa/drivers/dri/i965/intel_tex.c
@@ -335,7 +335,8 @@ intel_set_texture_storage_for_buffer_object(struct gl_context *ctx,
struct brw_bo *bo = intel_bufferobj_buffer(brw, intel_buffer_obj,
buffer_offset,
- row_stride * image->Height);
+ row_stride * image->Height,
+ !read_only);
intel_texobj->mt =
intel_miptree_create_for_bo(brw, bo,
image->TexFormat,
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 19:43:31 +0000