diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/intel/genxml/gen10.xml | 4 | ||||
| -rw-r--r-- | src/intel/genxml/gen11.xml | 4 | ||||
| -rw-r--r-- | src/intel/genxml/gen4.xml | 4 | ||||
| -rw-r--r-- | src/intel/genxml/gen45.xml | 4 | ||||
| -rw-r--r-- | src/intel/genxml/gen5.xml | 4 | ||||
| -rw-r--r-- | src/intel/genxml/gen6.xml | 4 | ||||
| -rw-r--r-- | src/intel/genxml/gen7.xml | 4 | ||||
| -rw-r--r-- | src/intel/genxml/gen75.xml | 4 | ||||
| -rw-r--r-- | src/intel/genxml/gen8.xml | 4 | ||||
| -rw-r--r-- | src/intel/genxml/gen9.xml | 4 |
10 files changed, 40 insertions, 0 deletions
diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml index bd914ad10ee..8c35d70e9d2 100644 --- a/src/intel/genxml/gen10.xml +++ b/src/intel/genxml/gen10.xml @@ -2969,6 +2969,10 @@ <field name="DWord Length" start="0" end="7" type="uint" default="1"/> <field name="Register Offset" start="34" end="54" type="offset"/> <field name="Data DWord" start="64" end="95" type="uint"/> + <group count="0" start="96" size="64"> + <field name="Register Offset" start="2" end="22" type="offset"/> + <field name="Data DWord" start="32" end="63" type="uint"/> + </group> </instruction> <instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="4"> diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml index cb3212620f5..517f0beb93b 100644 --- a/src/intel/genxml/gen11.xml +++ b/src/intel/genxml/gen11.xml @@ -2956,6 +2956,10 @@ <field name="DWord Length" start="0" end="7" type="uint" default="1"/> <field name="Register Offset" start="34" end="54" type="offset"/> <field name="Data DWord" start="64" end="95" type="uint"/> + <group count="0" start="96" size="64"> + <field name="Register Offset" start="2" end="22" type="offset"/> + <field name="Data DWord" start="32" end="63" type="uint"/> + </group> </instruction> <instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="4"> diff --git a/src/intel/genxml/gen4.xml b/src/intel/genxml/gen4.xml index e1ca810f236..6f513c5833b 100644 --- a/src/intel/genxml/gen4.xml +++ b/src/intel/genxml/gen4.xml @@ -860,6 +860,10 @@ <field name="DWord Length" start="0" end="5" type="uint" default="1"/> <field name="Register Offset" start="34" end="63" type="offset"/> <field name="Data DWord" start="64" end="95" type="uint"/> + <group count="0" start="96" size="64"> + <field name="Register Offset" start="2" end="31" type="offset"/> + <field name="Data DWord" start="32" end="63" type="uint"/> + </group> </instruction> <instruction name="MI_STORE_DATA_IMM" bias="2" length="5"> diff --git a/src/intel/genxml/gen45.xml b/src/intel/genxml/gen45.xml index 91dc3634801..fbd57a00c50 100644 --- a/src/intel/genxml/gen45.xml +++ b/src/intel/genxml/gen45.xml @@ -890,6 +890,10 @@ <field name="DWord Length" start="0" end="5" type="uint" default="1"/> <field name="Register Offset" start="34" end="63" type="offset"/> <field name="Data DWord" start="64" end="95" type="uint"/> + <group count="0" start="96" size="64"> + <field name="Register Offset" start="2" end="31" type="offset"/> + <field name="Data DWord" start="32" end="63" type="uint"/> + </group> </instruction> <instruction name="MI_STORE_DATA_IMM" bias="2" length="5"> diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml index 650692f6bda..5c93ecdda30 100644 --- a/src/intel/genxml/gen5.xml +++ b/src/intel/genxml/gen5.xml @@ -974,6 +974,10 @@ <field name="DWord Length" start="0" end="5" type="uint" default="1"/> <field name="Register Offset" start="34" end="63" type="offset"/> <field name="Data DWord" start="64" end="95" type="uint"/> + <group count="0" start="96" size="64"> + <field name="Register Offset" start="2" end="31" type="offset"/> + <field name="Data DWord" start="32" end="63" type="uint"/> + </group> </instruction> <instruction name="MI_STORE_DATA_IMM" bias="2" length="5"> diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml index 08779733dbd..0493221bd72 100644 --- a/src/intel/genxml/gen6.xml +++ b/src/intel/genxml/gen6.xml @@ -1531,6 +1531,10 @@ <field name="DWord Length" start="0" end="7" type="uint" default="1"/> <field name="Register Offset" start="34" end="54" type="offset"/> <field name="Data DWord" start="64" end="95" type="uint"/> + <group count="0" start="96" size="64"> + <field name="Register Offset" start="2" end="22" type="offset"/> + <field name="Data DWord" start="32" end="63" type="uint"/> + </group> </instruction> <instruction name="MI_LOAD_SCAN_LINES_EXCL" bias="2" length="2"> diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml index 4865843fcbb..baf42a7d32d 100644 --- a/src/intel/genxml/gen7.xml +++ b/src/intel/genxml/gen7.xml @@ -2020,6 +2020,10 @@ <field name="DWord Length" start="0" end="7" type="uint" default="1"/> <field name="Register Offset" start="34" end="54" type="offset"/> <field name="Data DWord" start="64" end="95" type="uint"/> + <group count="0" start="96" size="64"> + <field name="Register Offset" start="2" end="22" type="offset"/> + <field name="Data DWord" start="32" end="63" type="uint"/> + </group> </instruction> <instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="3"> diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml index da06e84ee91..7b635b22dac 100644 --- a/src/intel/genxml/gen75.xml +++ b/src/intel/genxml/gen75.xml @@ -2380,6 +2380,10 @@ <field name="DWord Length" start="0" end="7" type="uint" default="1"/> <field name="Register Offset" start="34" end="54" type="offset"/> <field name="Data DWord" start="64" end="95" type="uint"/> + <group count="0" start="96" size="64"> + <field name="Register Offset" start="2" end="22" type="offset"/> + <field name="Data DWord" start="32" end="63" type="uint"/> + </group> </instruction> <instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="3"> diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml index 28fbdfdf09a..0f3757034f3 100644 --- a/src/intel/genxml/gen8.xml +++ b/src/intel/genxml/gen8.xml @@ -2607,6 +2607,10 @@ <field name="DWord Length" start="0" end="7" type="uint" default="1"/> <field name="Register Offset" start="34" end="54" type="offset"/> <field name="Data DWord" start="64" end="95" type="uint"/> + <group count="0" start="64" size="64"> + <field name="Register Offset" start="2" end="22" type="offset"/> + <field name="Data DWord" start="32" end="63" type="uint"/> + </group> </instruction> <instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="4"> diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml index 0912b6f7fe4..7d3c74de74c 100644 --- a/src/intel/genxml/gen9.xml +++ b/src/intel/genxml/gen9.xml @@ -2894,6 +2894,10 @@ <field name="DWord Length" start="0" end="7" type="uint" default="1"/> <field name="Register Offset" start="34" end="54" type="offset"/> <field name="Data DWord" start="64" end="95" type="uint"/> + <group count="0" start="96" size="64"> + <field name="Register Offset" start="2" end="22" type="offset"/> + <field name="Data DWord" start="32" end="63" type="uint"/> + </group> </instruction> <instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="4"> |