diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/ilo/ilo_builder.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/ilo/ilo_draw.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/ilo/ilo_render.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/ilo/ilo_resource.c | 33 | ||||
| -rw-r--r-- | src/gallium/drivers/ilo/intel_winsys.h | 40 | ||||
| -rw-r--r-- | src/gallium/winsys/intel/drm/intel_drm_winsys.c | 72 |
6 files changed, 71 insertions, 80 deletions
diff --git a/src/gallium/drivers/ilo/ilo_builder.c b/src/gallium/drivers/ilo/ilo_builder.c index 92a129030e9..52c4b218435 100644 --- a/src/gallium/drivers/ilo/ilo_builder.c +++ b/src/gallium/drivers/ilo/ilo_builder.c @@ -139,7 +139,7 @@ alloc_writer_bo(struct intel_winsys *winsys, [ILO_BUILDER_WRITER_INSTRUCTION] = "instruction", }; - return intel_winsys_alloc_buffer(winsys, writer_names[which], size, true); + return intel_winsys_alloc_bo(winsys, writer_names[which], size, true); } static void * diff --git a/src/gallium/drivers/ilo/ilo_draw.c b/src/gallium/drivers/ilo/ilo_draw.c index 9d1c419dd2a..02e5225f4cd 100644 --- a/src/gallium/drivers/ilo/ilo_draw.c +++ b/src/gallium/drivers/ilo/ilo_draw.c @@ -183,7 +183,7 @@ ilo_init_draw_query(struct ilo_context *ilo, struct ilo_query *q) q->stride <<= q->in_pairs; bo_size = (q->stride > 4096) ? q->stride : 4096; - q->bo = intel_winsys_alloc_buffer(ilo->winsys, "query", bo_size, false); + q->bo = intel_winsys_alloc_bo(ilo->winsys, "query", bo_size, false); if (!q->bo) return false; diff --git a/src/gallium/drivers/ilo/ilo_render.c b/src/gallium/drivers/ilo/ilo_render.c index c1ed2c37a3e..c5492562de0 100644 --- a/src/gallium/drivers/ilo/ilo_render.c +++ b/src/gallium/drivers/ilo/ilo_render.c @@ -113,7 +113,7 @@ ilo_render_create(struct ilo_builder *builder) render->dev = builder->dev; render->builder = builder; - render->workaround_bo = intel_winsys_alloc_buffer(builder->winsys, + render->workaround_bo = intel_winsys_alloc_bo(builder->winsys, "PIPE_CONTROL workaround", 4096, false); if (!render->workaround_bo) { ilo_warn("failed to allocate PIPE_CONTROL workaround bo\n"); diff --git a/src/gallium/drivers/ilo/ilo_resource.c b/src/gallium/drivers/ilo/ilo_resource.c index 6dfc5801687..9f4ee4012c1 100644 --- a/src/gallium/drivers/ilo/ilo_resource.c +++ b/src/gallium/drivers/ilo/ilo_resource.c @@ -185,16 +185,24 @@ tex_create_bo(struct ilo_texture *tex) struct ilo_screen *is = ilo_screen(tex->base.screen); const char *name = resource_get_bo_name(&tex->base); const bool cpu_init = resource_get_cpu_init(&tex->base); - enum intel_tiling_mode tiling; + struct intel_bo *bo; - /* no native support */ - if (tex->layout.tiling == GEN8_TILING_W) - tiling = INTEL_TILING_NONE; - else - tiling = surface_to_winsys_tiling(tex->layout.tiling); + bo = intel_winsys_alloc_bo(is->winsys, name, + tex->layout.bo_stride * tex->layout.bo_height, cpu_init); + + /* set the tiling for transfer and export */ + if (bo && (tex->layout.tiling == GEN6_TILING_X || + tex->layout.tiling == GEN6_TILING_Y)) { + const enum intel_tiling_mode tiling = + surface_to_winsys_tiling(tex->layout.tiling); + + if (intel_bo_set_tiling(bo, tiling, tex->layout.bo_stride)) { + intel_bo_unreference(bo); + bo = NULL; + } + } - tex->bo = intel_winsys_alloc_bo(is->winsys, name, tiling, - tex->layout.bo_stride, tex->layout.bo_height, cpu_init); + tex->bo = bo; return (tex->bo != NULL); } @@ -230,7 +238,7 @@ tex_create_hiz(struct ilo_texture *tex) struct ilo_screen *is = ilo_screen(tex->base.screen); unsigned lv; - tex->aux_bo = intel_winsys_alloc_buffer(is->winsys, "hiz texture", + tex->aux_bo = intel_winsys_alloc_bo(is->winsys, "hiz texture", tex->layout.aux_stride * tex->layout.aux_height, false); if (!tex->aux_bo) return false; @@ -259,7 +267,7 @@ tex_create_mcs(struct ilo_texture *tex) assert(tex->layout.aux_enables == (1 << (tex->base.last_level + 1)) - 1); - tex->aux_bo = intel_winsys_alloc_buffer(is->winsys, "mcs texture", + tex->aux_bo = intel_winsys_alloc_bo(is->winsys, "mcs texture", tex->layout.aux_stride * tex->layout.aux_height, false); if (!tex->aux_bo) return false; @@ -383,7 +391,7 @@ tex_get_handle(struct ilo_texture *tex, struct winsys_handle *handle) enum intel_tiling_mode tiling; int err; - /* no native support */ + /* must match what tex_create_bo() sets */ if (tex->layout.tiling == GEN8_TILING_W) tiling = INTEL_TILING_NONE; else @@ -402,8 +410,7 @@ buf_create_bo(struct ilo_buffer *buf) const char *name = resource_get_bo_name(&buf->base); const bool cpu_init = resource_get_cpu_init(&buf->base); - buf->bo = intel_winsys_alloc_buffer(is->winsys, name, - buf->bo_size, cpu_init); + buf->bo = intel_winsys_alloc_bo(is->winsys, name, buf->bo_size, cpu_init); return (buf->bo != NULL); } diff --git a/src/gallium/drivers/ilo/intel_winsys.h b/src/gallium/drivers/ilo/intel_winsys.h index 5a199e2e819..77eb030efad 100644 --- a/src/gallium/drivers/ilo/intel_winsys.h +++ b/src/gallium/drivers/ilo/intel_winsys.h @@ -126,43 +126,24 @@ intel_winsys_get_reset_stats(struct intel_winsys *winsys, * Allocate a buffer object. * * \param name Informative description of the bo. - * \param tiling Tiling mode. - * \param pitch Pitch of the bo. - * \param height Height of the bo. + * \param size Size of the bo. * \param cpu_init Will be initialized by CPU. */ struct intel_bo * intel_winsys_alloc_bo(struct intel_winsys *winsys, const char *name, - enum intel_tiling_mode tiling, - unsigned long pitch, - unsigned long height, + unsigned long size, bool cpu_init); /** - * Allocate a linear buffer object. - */ -static inline struct intel_bo * -intel_winsys_alloc_buffer(struct intel_winsys *winsys, - const char *name, - unsigned long size, - bool cpu_init) -{ - return intel_winsys_alloc_bo(winsys, name, - INTEL_TILING_NONE, size, 1, cpu_init); -} - -/** - * Create a bo from a user memory pointer. Both \p userptr and (\p pitch * \p - * height) must be page aligned. + * Create a bo from a user memory pointer. Both \p userptr and \p size must + * be page aligned. */ struct intel_bo * intel_winsys_import_userptr(struct intel_winsys *winsys, const char *name, void *userptr, - enum intel_tiling_mode tiling, - unsigned long pitch, - unsigned long height, + unsigned long size, unsigned long flags); /** @@ -177,7 +158,8 @@ intel_winsys_import_handle(struct intel_winsys *winsys, unsigned long *pitch); /** - * Export \p bo as a winsys handle for inter-process sharing. + * Export \p bo as a winsys handle for inter-process sharing. \p tiling and + * \p pitch must match those set by \p intel_bo_set_tiling(). */ int intel_winsys_export_handle(struct intel_winsys *winsys, @@ -234,6 +216,14 @@ void intel_bo_unreference(struct intel_bo *bo); /** + * Set the tiling of \p bo. The info is used by GTT mapping and bo export. + */ +int +intel_bo_set_tiling(struct intel_bo *bo, + enum intel_tiling_mode tiling, + unsigned long pitch); + +/** * Map \p bo for CPU access. Recursive mapping is allowed. * * map() maps the backing store into CPU address space, cached. It will block diff --git a/src/gallium/winsys/intel/drm/intel_drm_winsys.c b/src/gallium/winsys/intel/drm/intel_drm_winsys.c index a41cbb04d72..d05e0362a6c 100644 --- a/src/gallium/winsys/intel/drm/intel_drm_winsys.c +++ b/src/gallium/winsys/intel/drm/intel_drm_winsys.c @@ -275,53 +275,19 @@ intel_winsys_get_reset_stats(struct intel_winsys *winsys, struct intel_bo * intel_winsys_alloc_bo(struct intel_winsys *winsys, const char *name, - enum intel_tiling_mode tiling, - unsigned long pitch, - unsigned long height, + unsigned long size, bool cpu_init) { const unsigned int alignment = 4096; /* always page-aligned */ - unsigned long size; drm_intel_bo *bo; - switch (tiling) { - case INTEL_TILING_X: - if (pitch % 512) - return NULL; - break; - case INTEL_TILING_Y: - if (pitch % 128) - return NULL; - break; - default: - break; - } - - if (pitch > ULONG_MAX / height) - return NULL; - - size = pitch * height; - if (cpu_init) { bo = drm_intel_bo_alloc(winsys->bufmgr, name, size, alignment); - } - else { + } else { bo = drm_intel_bo_alloc_for_render(winsys->bufmgr, name, size, alignment); } - if (bo && tiling != INTEL_TILING_NONE) { - uint32_t real_tiling = tiling; - int err; - - err = drm_intel_bo_set_tiling(bo, &real_tiling, pitch); - if (err || real_tiling != tiling) { - assert(!"tiling mismatch"); - drm_intel_bo_unreference(bo); - return NULL; - } - } - return (struct intel_bo *) bo; } @@ -329,9 +295,7 @@ struct intel_bo * intel_winsys_import_userptr(struct intel_winsys *winsys, const char *name, void *userptr, - enum intel_tiling_mode tiling, - unsigned long pitch, - unsigned long height, + unsigned long size, unsigned long flags) { return NULL; @@ -512,6 +476,36 @@ intel_bo_unreference(struct intel_bo *bo) drm_intel_bo_unreference(gem_bo(bo)); } +int +intel_bo_set_tiling(struct intel_bo *bo, + enum intel_tiling_mode tiling, + unsigned long pitch) +{ + uint32_t real_tiling = tiling; + int err; + + switch (tiling) { + case INTEL_TILING_X: + if (pitch % 512) + return -1; + break; + case INTEL_TILING_Y: + if (pitch % 128) + return -1; + break; + default: + break; + } + + err = drm_intel_bo_set_tiling(gem_bo(bo), &real_tiling, pitch); + if (err || real_tiling != tiling) { + assert(!"tiling mismatch"); + return -1; + } + + return 0; +} + void * intel_bo_map(struct intel_bo *bo, bool write_enable) { |