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-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 64752dd0b86..0e3888f3fbb 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -488,6 +488,13 @@ intel_miptree_choose_tiling(struct brw_context *brw,
base_format == GL_DEPTH_STENCIL_EXT)
return I915_TILING_Y;
+ /* 1D textures (and 1D array textures) don't get any benefit from tiling,
+ * in fact it leads to a less efficient use of memory space and bandwidth
+ * due to tile alignment.
+ */
+ if (mt->logical_height0 == 1)
+ return I915_TILING_NONE;
+
int minimum_pitch = mt->total_width * mt->cpp;
/* If the width is much smaller than a tile, don't bother tiling. */