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-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.cpp63
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.h1
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm.c65
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm.h2
4 files changed, 63 insertions, 68 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 2f88d92e3bd..1aa9710ba4d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1964,13 +1964,74 @@ fs_visitor::get_instruction_generating_reg(fs_inst *start,
}
}
+void
+fs_visitor::setup_payload_gen6()
+{
+ struct intel_context *intel = &brw->intel;
+ bool uses_depth =
+ (fp->Base.InputsRead & (1 << FRAG_ATTRIB_WPOS)) != 0;
+ unsigned barycentric_interp_modes = c->prog_data.barycentric_interp_modes;
+
+ assert(intel->gen >= 6);
+
+ /* R0-1: masks, pixel X/Y coordinates. */
+ c->nr_payload_regs = 2;
+ /* R2: only for 32-pixel dispatch.*/
+
+ /* R3-26: barycentric interpolation coordinates. These appear in the
+ * same order that they appear in the brw_wm_barycentric_interp_mode
+ * enum. Each set of coordinates occupies 2 registers if dispatch width
+ * == 8 and 4 registers if dispatch width == 16. Coordinates only
+ * appear if they were enabled using the "Barycentric Interpolation
+ * Mode" bits in WM_STATE.
+ */
+ for (int i = 0; i < BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT; ++i) {
+ if (barycentric_interp_modes & (1 << i)) {
+ c->barycentric_coord_reg[i] = c->nr_payload_regs;
+ c->nr_payload_regs += 2;
+ if (c->dispatch_width == 16) {
+ c->nr_payload_regs += 2;
+ }
+ }
+ }
+
+ /* R27: interpolated depth if uses source depth */
+ if (uses_depth) {
+ c->source_depth_reg = c->nr_payload_regs;
+ c->nr_payload_regs++;
+ if (c->dispatch_width == 16) {
+ /* R28: interpolated depth if not 8-wide. */
+ c->nr_payload_regs++;
+ }
+ }
+ /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
+ if (uses_depth) {
+ c->source_w_reg = c->nr_payload_regs;
+ c->nr_payload_regs++;
+ if (c->dispatch_width == 16) {
+ /* R30: interpolated W if not 8-wide. */
+ c->nr_payload_regs++;
+ }
+ }
+ /* R31: MSAA position offsets. */
+ /* R32-: bary for 32-pixel. */
+ /* R58-59: interp W for 32-pixel. */
+
+ if (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
+ c->source_depth_to_render_target = true;
+ }
+}
+
bool
fs_visitor::run()
{
uint32_t prog_offset_16 = 0;
uint32_t orig_nr_params = c->prog_data.nr_params;
- brw_wm_payload_setup(brw, c);
+ if (intel->gen >= 6)
+ setup_payload_gen6();
+ else
+ brw_wm_lookup_iz(intel, c);
if (c->dispatch_width == 16) {
/* We have to do a compaction pass now, or the one at the end of
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 389643eafef..fbe4c1aa2f4 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -249,6 +249,7 @@ public:
fs_reg reg);
bool run();
+ void setup_payload_gen6();
void setup_paramvalues_refs();
void assign_curb_setup();
void calculate_urb_setup();
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index 9b2c58c3aa3..00bd3fe0eb5 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -101,71 +101,6 @@ brw_compute_barycentric_interp_modes(struct brw_context *brw,
return barycentric_interp_modes;
}
-
-void
-brw_wm_payload_setup(struct brw_context *brw,
- struct brw_wm_compile *c)
-{
- struct intel_context *intel = &brw->intel;
- bool uses_depth = (c->fp->program.Base.InputsRead &
- (1 << FRAG_ATTRIB_WPOS)) != 0;
- unsigned barycentric_interp_modes = c->prog_data.barycentric_interp_modes;
- int i;
-
- if (intel->gen >= 6) {
- /* R0-1: masks, pixel X/Y coordinates. */
- c->nr_payload_regs = 2;
- /* R2: only for 32-pixel dispatch.*/
-
- /* R3-26: barycentric interpolation coordinates. These appear in the
- * same order that they appear in the brw_wm_barycentric_interp_mode
- * enum. Each set of coordinates occupies 2 registers if dispatch width
- * == 8 and 4 registers if dispatch width == 16. Coordinates only
- * appear if they were enabled using the "Barycentric Interpolation
- * Mode" bits in WM_STATE.
- */
- for (i = 0; i < BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT; ++i) {
- if (barycentric_interp_modes & (1 << i)) {
- c->barycentric_coord_reg[i] = c->nr_payload_regs;
- c->nr_payload_regs += 2;
- if (c->dispatch_width == 16) {
- c->nr_payload_regs += 2;
- }
- }
- }
-
- /* R27: interpolated depth if uses source depth */
- if (uses_depth) {
- c->source_depth_reg = c->nr_payload_regs;
- c->nr_payload_regs++;
- if (c->dispatch_width == 16) {
- /* R28: interpolated depth if not 8-wide. */
- c->nr_payload_regs++;
- }
- }
- /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W.
- */
- if (uses_depth) {
- c->source_w_reg = c->nr_payload_regs;
- c->nr_payload_regs++;
- if (c->dispatch_width == 16) {
- /* R30: interpolated W if not 8-wide. */
- c->nr_payload_regs++;
- }
- }
- /* R31: MSAA position offsets. */
- /* R32-: bary for 32-pixel. */
- /* R58-59: interp W for 32-pixel. */
-
- if (c->fp->program.Base.OutputsWritten &
- BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
- c->source_depth_to_render_target = true;
- }
- } else {
- brw_wm_lookup_iz(intel, c);
- }
-}
-
bool
brw_wm_prog_data_compare(const void *in_a, const void *in_b,
int aux_size, const void *in_key)
diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h
index c017866c421..7b5f44ffb61 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.h
+++ b/src/mesa/drivers/dri/i965/brw_wm.h
@@ -110,8 +110,6 @@ struct gl_shader_program *brw_new_shader_program(struct gl_context *ctx, GLuint
bool brw_color_buffer_write_enabled(struct brw_context *brw);
bool brw_render_target_supported(struct intel_context *intel,
struct gl_renderbuffer *rb);
-void brw_wm_payload_setup(struct brw_context *brw,
- struct brw_wm_compile *c);
bool do_wm_prog(struct brw_context *brw,
struct gl_shader_program *prog,
struct brw_fragment_program *fp,
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 00:25:21 +0000