diff options
Diffstat (limited to 'src')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.h | 2 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_misc_state.c | 23 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_state.h | 12 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 5 |
4 files changed, 36 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 1d5ef82abe3..542ec3d030f 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1148,6 +1148,8 @@ struct brw_context struct brw_state_flags pipelines[BRW_NUM_PIPELINES]; } state; + enum brw_pipeline last_pipeline; + struct brw_cache cache; /** IDs for meta stencil blit shader programs. */ diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 78a46cb050d..67a693b5ec1 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -854,6 +854,22 @@ const struct brw_tracked_state brw_line_stipple = { }; +void +brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline) +{ + const bool is_965 = brw->gen == 4 && !brw->is_g4x; + const uint32_t _3DSTATE_PIPELINE_SELECT = + is_965 ? CMD_PIPELINE_SELECT_965 : CMD_PIPELINE_SELECT_GM45; + + /* Select the pipeline */ + BEGIN_BATCH(1); + OUT_BATCH(_3DSTATE_PIPELINE_SELECT << 16 | + (brw->gen >= 9 ? (3 << 8) : 0) | + (pipeline == BRW_COMPUTE_PIPELINE ? 2 : 0)); + ADVANCE_BATCH(); +} + + /*********************************************************************** * Misc invariant state packets */ @@ -863,12 +879,7 @@ brw_upload_invariant_state(struct brw_context *brw) { const bool is_965 = brw->gen == 4 && !brw->is_g4x; - /* Select the 3D pipeline (as opposed to media) */ - const uint32_t _3DSTATE_PIPELINE_SELECT = - is_965 ? CMD_PIPELINE_SELECT_965 : CMD_PIPELINE_SELECT_GM45; - BEGIN_BATCH(1); - OUT_BATCH(_3DSTATE_PIPELINE_SELECT << 16 | (brw->gen >= 9 ? (3 << 8) : 0)); - ADVANCE_BATCH(); + brw_select_pipeline(brw, BRW_RENDER_PIPELINE); if (brw->gen < 6) { /* Disable depth offset clamping. */ diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index 565946d4667..5c27b3d367e 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -185,6 +185,18 @@ void brw_upload_compute_state(struct brw_context *brw); void brw_compute_state_finished(struct brw_context *brw); void brw_init_state(struct brw_context *brw); void brw_destroy_state(struct brw_context *brw); +void brw_emit_select_pipeline(struct brw_context *brw, + enum brw_pipeline pipeline); + +static inline void +brw_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline) +{ + if (unlikely(brw->last_pipeline != pipeline)) { + assert(pipeline < BRW_NUM_PIPELINES); + brw_emit_select_pipeline(brw, pipeline); + brw->last_pipeline = pipeline; + } +} /*********************************************************************** * brw_state_cache.c diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 15d6953a7ef..686a3da795a 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -406,6 +406,9 @@ void brw_init_state( struct brw_context *brw ) { struct gl_context *ctx = &brw->ctx; + /* Force the first brw_select_pipeline to emit pipeline select */ + brw->last_pipeline = BRW_NUM_PIPELINES; + STATIC_ASSERT(ARRAY_SIZE(gen4_atoms) <= ARRAY_SIZE(brw->render_atoms)); STATIC_ASSERT(ARRAY_SIZE(gen6_atoms) <= ARRAY_SIZE(brw->render_atoms)); STATIC_ASSERT(ARRAY_SIZE(gen7_render_atoms) <= @@ -656,6 +659,8 @@ brw_upload_pipeline_state(struct brw_context *brw, static int dirty_count = 0; struct brw_state_flags state = brw->state.pipelines[pipeline]; + brw_select_pipeline(brw, pipeline); + if (0) { /* Always re-emit all state. */ brw->NewGLState = ~0; |