diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_descriptors.c | 14 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/sid.h | 2 |
2 files changed, 14 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index c9599617ede..f0e353a1db9 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -167,8 +167,18 @@ static void si_update_descriptors(struct si_context *sctx, desc->atom.num_dw += 4; /* second pointer update */ desc->atom.dirty = true; + + /* TODO: Investigate if these flushes can be removed after + * adding CE support. */ + /* The descriptors are read with the K cache. */ sctx->b.flags |= SI_CONTEXT_INV_KCACHE; + + /* Since SI uses uncached CP DMA to update descriptors, + * we have to flush TC L2, which is used to fetch constants + * along with KCACHE. */ + if (sctx->b.chip_class == SI) + sctx->b.flags |= SI_CONTEXT_INV_TC_L2; } else { desc->atom.dirty = false; } @@ -248,7 +258,9 @@ static void si_emit_descriptors(struct si_context *sctx, packet_size = 2 + desc->element_dw_size; radeon_emit(cs, PKT3(PKT3_WRITE_DATA, packet_size, 0)); - radeon_emit(cs, PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_TC_OR_L2) | + radeon_emit(cs, PKT3_WRITE_DATA_DST_SEL(sctx->b.chip_class == SI ? + PKT3_WRITE_DATA_DST_SEL_MEM_SYNC : + PKT3_WRITE_DATA_DST_SEL_TC_L2) | PKT3_WRITE_DATA_WR_CONFIRM | PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME)); radeon_emit(cs, va & 0xFFFFFFFFUL); diff --git a/src/gallium/drivers/radeonsi/sid.h b/src/gallium/drivers/radeonsi/sid.h index c78ba7c2991..e36244dc7d4 100644 --- a/src/gallium/drivers/radeonsi/sid.h +++ b/src/gallium/drivers/radeonsi/sid.h @@ -98,7 +98,7 @@ #define PKT3_WRITE_DATA_DST_SEL(x) ((x) << 8) #define PKT3_WRITE_DATA_DST_SEL_REG 0 #define PKT3_WRITE_DATA_DST_SEL_MEM_SYNC 1 -#define PKT3_WRITE_DATA_DST_SEL_TC_OR_L2 2 +#define PKT3_WRITE_DATA_DST_SEL_TC_L2 2 #define PKT3_WRITE_DATA_DST_SEL_GDS 3 #define PKT3_WRITE_DATA_DST_SEL_RESERVED_4 4 #define PKT3_WRITE_DATA_DST_SEL_MEM_ASYNC 5 |