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-rw-r--r--src/mesa/drivers/dri/i965/Makefile3
-rw-r--r--src/mesa/drivers/dri/i965/brw_defines.h62
-rw-r--r--src/mesa/drivers/dri/i965/brw_state.h1
-rw-r--r--src/mesa/drivers/dri/i965/brw_state_upload.c2
-rw-r--r--src/mesa/drivers/dri/i965/gen6_wm_state.c162
5 files changed, 228 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index d614fbb6a9b..f84e87e7e64 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -93,7 +93,8 @@ DRIVER_SOURCES = \
gen6_sf_state.c \
gen6_urb.c \
gen6_viewport_state.c \
- gen6_vs_state.c
+ gen6_vs_state.c \
+ gen6_wm_state.c
C_SOURCES = \
$(COMMON_SOURCES) \
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index f34575355e4..be32a8fa828 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -955,8 +955,70 @@
/* DW18: attr 0-7 wrap shortest enables */
/* DW19: attr 8-16 wrap shortest enables */
+#define CMD_3D_WM_STATE 0x7814 /* GEN6+ */
+/* DW1: kernel pointer */
+/* DW2 */
+# define GEN6_WM_SPF_MODE (1 << 31)
+# define GEN6_WM_VECTOR_MASK_ENABLE (1 << 30)
+# define GEN6_WM_SAMPLER_COUNT_SHIFT 27
+# define GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT 18
+/* DW3: scratch space */
+/* DW4 */
+# define GEN6_WM_STATISTICS_ENABLE (1 << 31)
+# define GEN6_WM_DEPTH_CLEAR (1 << 30)
+# define GEN6_WM_DEPTH_RESOLVE (1 << 28)
+# define GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE (1 << 27)
+# define GEN6_WM_DISPATCH_START_GRF_SHIFT_0 16
+# define GEN6_WM_DISPATCH_START_GRF_SHIFT_1 8
+# define GEN6_WM_DISPATCH_START_GRF_SHIFT_2 0
+/* DW5 */
+# define GEN6_WM_MAX_THREADS_SHIFT 25
+# define GEN6_WM_KILL_ENABLE (1 << 22)
+# define GEN6_WM_COMPUTED_DEPTH (1 << 21)
+# define GEN6_WM_USES_SOURCE_DEPTH (1 << 20)
+# define GEN6_WM_DISPATCH_ENABLE (1 << 19)
+# define GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5 (0 << 16)
+# define GEN6_WM_LINE_END_CAP_AA_WIDTH_1_0 (1 << 16)
+# define GEN6_WM_LINE_END_CAP_AA_WIDTH_2_0 (2 << 16)
+# define GEN6_WM_LINE_END_CAP_AA_WIDTH_4_0 (3 << 16)
+# define GEN6_WM_LINE_AA_WIDTH_0_5 (0 << 14)
+# define GEN6_WM_LINE_AA_WIDTH_1_0 (1 << 14)
+# define GEN6_WM_LINE_AA_WIDTH_2_0 (2 << 14)
+# define GEN6_WM_LINE_AA_WIDTH_4_0 (3 << 14)
+# define GEN6_WM_POLYGON_STIPPLE_ENABLE (1 << 13)
+# define GEN6_WM_LINE_STIPPLE_ENABLE (1 << 12)
+# define GEN6_WM_OMASK_TO_RENDER_TARGET (1 << 9)
+# define GEN6_WM_USES_SOURCE_W (1 << 8)
+# define GEN6_WM_DUAL_SOURCE_BLEND_ENABLE (1 << 7)
+# define GEN6_WM_32_DISPATCH_ENABLE (1 << 2)
+# define GEN6_WM_16_DISPATCH_ENABLE (1 << 1)
+# define GEN6_WM_8_DISPATCH_ENABLE (1 << 0)
+/* DW6 */
+# define GEN6_WM_NUM_SF_OUTPUTS_SHIFT 20
+# define GEN6_WM_POSOFFSET_NONE (0 << 18)
+# define GEN6_WM_POSOFFSET_CENTROID (2 << 18)
+# define GEN6_WM_POSOFFSET_SAMPLE (3 << 18)
+# define GEN6_WM_POSITION_ZW_PIXEL (0 << 16)
+# define GEN6_WM_POSITION_ZW_CENTROID (2 << 16)
+# define GEN6_WM_POSITION_ZW_SAMPLE (3 << 16)
+# define GEN6_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 15)
+# define GEN6_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC (1 << 14)
+# define GEN6_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC (1 << 13)
+# define GEN6_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 12)
+# define GEN6_WM_PERSPECTIVE_CENTROID_BARYCENTRIC (1 << 11)
+# define GEN6_WM_PERSPECTIVE_PIXEL_BARYCENTRIC (1 << 10)
+# define GEN6_WM_POINT_RASTRULE_UPPER_RIGHT (1 << 9)
+# define GEN6_WM_MSRAST_OFF_PIXEL (0 << 1)
+# define GEN6_WM_MSRAST_OFF_PATTERN (1 << 1)
+# define GEN6_WM_MSRAST_ON_PIXEL (2 << 1)
+# define GEN6_WM_MSRAST_ON_PATTERN (3 << 1)
+# define GEN6_WM_MSDISPMODE_PERPIXEL (1 << 0)
+/* DW7: kernel 1 pointer */
+/* DW8: kernel 2 pointer */
+
#define CMD_3D_CONSTANT_VS_STATE 0x7815 /* GEN6+ */
#define CMD_3D_CONSTANT_GS_STATE 0x7816 /* GEN6+ */
+#define CMD_3D_CONSTANT_PS_STATE 0x7817 /* GEN6+ */
# define GEN6_CONSTANT_BUFFER_3_ENABLE (1 << 15)
# define GEN6_CONSTANT_BUFFER_2_ENABLE (1 << 14)
# define GEN6_CONSTANT_BUFFER_1_ENABLE (1 << 13)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index f2579d7cdc9..990eaf7e67f 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -105,6 +105,7 @@ const struct brw_tracked_state gen6_sf_vp;
const struct brw_tracked_state gen6_urb;
const struct brw_tracked_state gen6_viewport_state;
const struct brw_tracked_state gen6_vs_state;
+const struct brw_tracked_state gen6_wm_state;
/**
* Use same key for WM and VS surfaces.
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 6f214b037e9..824502ca6eb 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -134,7 +134,7 @@ const struct brw_tracked_state *gen6_atoms[] =
&gen6_gs_state,
&gen6_clip_state,
&gen6_sf_state,
- /* &gen6_wm_state, */
+ &gen6_wm_state,
&gen6_scissor_state,
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
new file mode 100644
index 00000000000..d896f7dcc0f
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright © 2009 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Eric Anholt <[email protected]>
+ *
+ */
+
+#include "brw_context.h"
+#include "brw_state.h"
+#include "brw_defines.h"
+#include "brw_util.h"
+#include "main/macros.h"
+#include "main/enums.h"
+#include "shader/prog_parameter.h"
+#include "shader/prog_statevars.h"
+#include "intel_batchbuffer.h"
+
+static void
+upload_wm_state(struct brw_context *brw)
+{
+ struct intel_context *intel = &brw->intel;
+ GLcontext *ctx = &intel->ctx;
+ const struct brw_fragment_program *fp =
+ brw_fragment_program_const(brw->fragment_program);
+ unsigned int nr_params = fp->program.Base.Parameters->NumParameters;
+ drm_intel_bo *constant_bo;
+ int i;
+ uint32_t dw2, dw4, dw5, dw6;
+
+ dw2 = dw4 = dw5 = dw6 = 0;
+ dw4 |= GEN6_WM_STATISTICS_ENABLE;
+ dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
+ dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
+
+ /* BRW_NEW_NR_SURFACES */
+ dw2 |= brw->wm.nr_surfaces << GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT;
+
+ /* CACHE_NEW_SAMPLER */
+ dw2 |= (ALIGN(brw->wm.sampler_count, 4) / 4) << GEN6_WM_SAMPLER_COUNT_SHIFT;
+ dw4 |= (1 << GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
+
+ dw5 |= (40 - 1) << GEN6_WM_MAX_THREADS_SHIFT;
+ dw5 |= GEN6_WM_DISPATCH_ENABLE;
+
+ /* BRW_NEW_FRAGMENT_PROGRAM */
+ if (fp->isGLSL)
+ dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
+ else
+ dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
+
+ /* _NEW_LINE */
+ if (ctx->Line.StippleFlag)
+ dw5 |= GEN6_WM_LINE_STIPPLE_ENABLE;
+
+ /* _NEW_POLYGONSTIPPLE */
+ if (ctx->Polygon.StippleFlag)
+ dw5 |= GEN6_WM_POLYGON_STIPPLE_ENABLE;
+
+ /* BRW_NEW_FRAGMENT_PROGRAM */
+ if (fp->program.Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
+ dw5 |= GEN6_WM_USES_SOURCE_DEPTH | GEN6_WM_USES_SOURCE_W;
+ if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
+ dw5 |= GEN6_WM_COMPUTED_DEPTH;
+
+ /* _NEW_COLOR */
+ if (fp->program.UsesKill || ctx->Color.AlphaEnabled)
+ dw5 |= GEN6_WM_KILL_ENABLE;
+
+ /* This should probably be FS inputs read */
+ dw6 |= brw_count_bits(brw->vs.prog_data->outputs_written) <<
+ GEN6_WM_NUM_SF_OUTPUTS_SHIFT;
+
+ BEGIN_BATCH(9);
+ OUT_BATCH(CMD_3D_WM_STATE << 16 | (9 - 2));
+ OUT_RELOC(brw->wm.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+ OUT_BATCH(dw2);
+ OUT_BATCH(0); /* scratch space base offset */
+ OUT_BATCH(dw4);
+ OUT_BATCH(dw5);
+ OUT_BATCH(dw6);
+ OUT_BATCH(0); /* kernel 1 pointer */
+ OUT_BATCH(0); /* kernel 2 pointer */
+ ADVANCE_BATCH();
+
+ intel_batchbuffer_emit_mi_flush(intel->batch);
+
+ if (fp->use_const_buffer || nr_params == 0) {
+ /* Disable the push constant buffers. */
+ BEGIN_BATCH(5);
+ OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 | (5 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+ } else {
+ /* Updates the ParamaterValues[i] pointers for all parameters of the
+ * basic type of PROGRAM_STATE_VAR.
+ */
+ _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
+
+ constant_bo = drm_intel_bo_alloc(intel->bufmgr, "WM constant_bo",
+ nr_params * 4 * sizeof(float),
+ 4096);
+ intel_bo_map_gtt_preferred(intel, constant_bo, GL_TRUE);
+ for (i = 0; i < nr_params; i++) {
+ memcpy((char *)constant_bo->virtual + i * 4 * sizeof(float),
+ fp->program.Base.Parameters->ParameterValues[i],
+ 4 * sizeof(float));
+ }
+ intel_bo_unmap_gtt_preferred(intel, constant_bo);
+
+ BEGIN_BATCH(5);
+ OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 |
+ GEN6_CONSTANT_BUFFER_0_ENABLE |
+ (5 - 2));
+ OUT_RELOC(constant_bo,
+ I915_GEM_DOMAIN_RENDER, 0, /* XXX: bad domain */
+ ALIGN(nr_params, 2) / 2 - 1);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+
+ drm_intel_bo_unreference(constant_bo);
+ }
+
+ intel_batchbuffer_emit_mi_flush(intel->batch);
+}
+
+const struct brw_tracked_state gen6_wm_state = {
+ .dirty = {
+ .mesa = _NEW_LINE | _NEW_POLYGONSTIPPLE | _NEW_COLOR,
+ .brw = (BRW_NEW_CURBE_OFFSETS |
+ BRW_NEW_FRAGMENT_PROGRAM |
+ BRW_NEW_NR_WM_SURFACES |
+ BRW_NEW_URB_FENCE |
+ BRW_NEW_BATCH),
+ .cache = CACHE_NEW_SAMPLER
+ },
+ .emit = upload_wm_state,
+};
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-21 11:05:21 +0000