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-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.cpp38
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.h1
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_visitor.cpp15
3 files changed, 28 insertions, 26 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 03d734f6e01..d083789b933 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1136,7 +1136,7 @@ fs_visitor::emit_general_interpolation(ir_variable *ir)
int location = ir->data.location;
for (unsigned int i = 0; i < array_elements; i++) {
for (unsigned int j = 0; j < type->matrix_columns; j++) {
- if (c->prog_data.urb_setup[location] == -1) {
+ if (prog_data->urb_setup[location] == -1) {
/* If there's no incoming setup data for this slot, don't
* emit interpolation for it.
*/
@@ -1447,12 +1447,12 @@ void
fs_visitor::assign_curb_setup()
{
if (dispatch_width == 8) {
- c->prog_data.first_curbe_grf = payload.num_regs;
+ prog_data->first_curbe_grf = payload.num_regs;
} else {
- c->prog_data.first_curbe_grf_16 = payload.num_regs;
+ prog_data->first_curbe_grf_16 = payload.num_regs;
}
- c->prog_data.curb_read_length = ALIGN(stage_prog_data->nr_params, 8) / 8;
+ prog_data->curb_read_length = ALIGN(stage_prog_data->nr_params, 8) / 8;
/* Map the offsets in the UNIFORM file to fixed HW regs. */
foreach_list(node, &this->instructions) {
@@ -1490,7 +1490,7 @@ void
fs_visitor::calculate_urb_setup()
{
for (unsigned int i = 0; i < VARYING_SLOT_MAX; i++) {
- c->prog_data.urb_setup[i] = -1;
+ prog_data->urb_setup[i] = -1;
}
int urb_next = 0;
@@ -1510,7 +1510,7 @@ fs_visitor::calculate_urb_setup()
for (unsigned int i = 0; i < VARYING_SLOT_MAX; i++) {
if (fp->Base.InputsRead & BRW_FS_VARYING_INPUT_MASK &
BITFIELD64_BIT(i)) {
- c->prog_data.urb_setup[i] = urb_next++;
+ prog_data->urb_setup[i] = urb_next++;
}
}
} else {
@@ -1533,7 +1533,7 @@ fs_visitor::calculate_urb_setup()
if (varying != BRW_VARYING_SLOT_COUNT &&
(fp->Base.InputsRead & BRW_FS_VARYING_INPUT_MASK &
BITFIELD64_BIT(varying))) {
- c->prog_data.urb_setup[varying] = slot - first_slot;
+ prog_data->urb_setup[varying] = slot - first_slot;
}
}
urb_next = prev_stage_vue_map.num_slots - first_slot;
@@ -1553,7 +1553,7 @@ fs_visitor::calculate_urb_setup()
* incremented, mapped or not.
*/
if (_mesa_varying_slot_in_fs((gl_varying_slot) i))
- c->prog_data.urb_setup[i] = urb_next;
+ prog_data->urb_setup[i] = urb_next;
urb_next++;
}
}
@@ -1565,16 +1565,16 @@ fs_visitor::calculate_urb_setup()
* See compile_sf_prog() for more info.
*/
if (fp->Base.InputsRead & BITFIELD64_BIT(VARYING_SLOT_PNTC))
- c->prog_data.urb_setup[VARYING_SLOT_PNTC] = urb_next++;
+ prog_data->urb_setup[VARYING_SLOT_PNTC] = urb_next++;
}
- c->prog_data.num_varying_inputs = urb_next;
+ prog_data->num_varying_inputs = urb_next;
}
void
fs_visitor::assign_urb_setup()
{
- int urb_start = payload.num_regs + c->prog_data.curb_read_length;
+ int urb_start = payload.num_regs + prog_data->curb_read_length;
/* Offset all the urb_setup[] index by the actual position of the
* setup regs, now that the location of the constants has been chosen.
@@ -1595,7 +1595,7 @@ fs_visitor::assign_urb_setup()
/* Each attribute is 4 setup channels, each of which is half a reg. */
this->first_non_payload_grf =
- urb_start + c->prog_data.num_varying_inputs * 2;
+ urb_start + prog_data->num_varying_inputs * 2;
}
/**
@@ -2797,7 +2797,7 @@ fs_visitor::setup_payload_gen6()
{
bool uses_depth =
(fp->Base.InputsRead & (1 << VARYING_SLOT_POS)) != 0;
- unsigned barycentric_interp_modes = c->prog_data.barycentric_interp_modes;
+ unsigned barycentric_interp_modes = prog_data->barycentric_interp_modes;
assert(brw->gen >= 6);
@@ -2841,9 +2841,9 @@ fs_visitor::setup_payload_gen6()
}
}
- c->prog_data.uses_pos_offset = c->key.compute_pos_offset;
+ prog_data->uses_pos_offset = c->key.compute_pos_offset;
/* R31: MSAA position offsets. */
- if (c->prog_data.uses_pos_offset) {
+ if (prog_data->uses_pos_offset) {
payload.sample_pos_reg = payload.num_regs;
payload.num_regs++;
}
@@ -2875,7 +2875,7 @@ fs_visitor::assign_binding_table_offsets()
/* If there are no color regions, we still perform an FB write to a null
* renderbuffer, which we place at surface index 0.
*/
- c->prog_data.binding_table.render_target_start = next_binding_table_offset;
+ prog_data->binding_table.render_target_start = next_binding_table_offset;
next_binding_table_offset += MAX2(c->key.nr_color_regions, 1);
assign_common_binding_table_offsets(next_binding_table_offset);
@@ -3084,13 +3084,13 @@ fs_visitor::run()
schedule_instructions(SCHEDULE_POST);
if (last_scratch > 0) {
- c->prog_data.total_scratch = brw_get_scratch_size(last_scratch);
+ prog_data->total_scratch = brw_get_scratch_size(last_scratch);
}
if (dispatch_width == 8)
- c->prog_data.reg_blocks = brw_register_blocks(grf_used);
+ prog_data->reg_blocks = brw_register_blocks(grf_used);
else
- c->prog_data.reg_blocks_16 = brw_register_blocks(grf_used);
+ prog_data->reg_blocks_16 = brw_register_blocks(grf_used);
/* If any state parameters were appended, then ParameterValues could have
* been realloced, in which case the driver uniform storage set up by
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 435d68caa60..d24f3f13d73 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -494,6 +494,7 @@ public:
struct gl_fragment_program *fp;
struct brw_wm_compile *c;
+ struct brw_wm_prog_data *prog_data;
unsigned int sanity_param_count;
int *param_size;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 646fbf591a8..a62ca9c5d1d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -751,7 +751,7 @@ fs_visitor::visit(ir_expression *ir)
*/
ir_constant *uniform_block = ir->operands[0]->as_constant();
ir_constant *const_offset = ir->operands[1]->as_constant();
- fs_reg surf_index = fs_reg(c->prog_data.base.binding_table.ubo_start +
+ fs_reg surf_index = fs_reg(prog_data->base.binding_table.ubo_start +
uniform_block->value.u[0]);
if (const_offset) {
fs_reg packed_consts = fs_reg(this, glsl_type::float_type);
@@ -2277,7 +2277,7 @@ fs_visitor::visit_atomic_counter_intrinsic(ir_call *ir)
ir_dereference *deref = static_cast<ir_dereference *>(
ir->actual_parameters.get_head());
ir_variable *location = deref->variable_referenced();
- unsigned surf_index = (c->prog_data.base.binding_table.abo_start +
+ unsigned surf_index = (prog_data->base.binding_table.abo_start +
location->data.atomic.buffer_index);
/* Calculate the surface offset */
@@ -2506,10 +2506,10 @@ fs_visitor::emit_dummy_fs()
struct brw_reg
fs_visitor::interp_reg(int location, int channel)
{
- int regnr = c->prog_data.urb_setup[location] * 2 + channel / 2;
+ int regnr = prog_data->urb_setup[location] * 2 + channel / 2;
int stride = (channel & 1) * 4;
- assert(c->prog_data.urb_setup[location] != -1);
+ assert(prog_data->urb_setup[location] != -1);
return brw_vec1_grf(regnr, stride);
}
@@ -2775,9 +2775,9 @@ fs_visitor::emit_fb_writes()
pop_force_uncompressed();
}
- c->prog_data.uses_omask =
+ prog_data->uses_omask =
fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK);
- if(c->prog_data.uses_omask) {
+ if (prog_data->uses_omask) {
this->current_annotation = "FB write oMask";
assert(this->sample_mask.file != BAD_FILE);
/* Hand over gl_SampleMask. Only lower 16 bits are relevant. */
@@ -2856,7 +2856,7 @@ fs_visitor::emit_fb_writes()
inst->flag_subreg = 1;
}
- c->prog_data.dual_src_blend = true;
+ prog_data->dual_src_blend = true;
this->current_annotation = NULL;
return;
}
@@ -2963,6 +2963,7 @@ fs_visitor::fs_visitor(struct brw_context *brw,
dispatch_width(dispatch_width)
{
this->c = c;
+ this->prog_data = &c->prog_data;
this->fp = fp;
this->mem_ctx = ralloc_context(NULL);
this->failed = false;
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-23 19:48:17 +0000