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-rw-r--r--src/mesa/drivers/dri/i965/brw_context.c5
-rw-r--r--src/mesa/drivers/dri/i965/brw_vtbl.c1
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 418c8737145..e94df2658ce 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -140,6 +140,11 @@ brwCreateContext(int api,
return false;
}
+ /* brwInitVtbl needs to know the chipset generation so that it can set the
+ * right pointers.
+ */
+ brw->intel.gen = screen->gen;
+
brwInitVtbl( brw );
brwInitDriverFunctions(screen, &functions);
diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c
index 9951e7da2cc..ca2e7a9a5ba 100644
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -249,6 +249,7 @@ void brwInitVtbl( struct brw_context *brw )
brw->intel.vtbl.render_target_supported = brw_render_target_supported;
brw->intel.vtbl.is_hiz_depth_format = brw_is_hiz_depth_format;
+ assert(brw->intel.gen >= 4);
if (brw->intel.gen >= 7) {
gen7_init_vtable_surface_functions(brw);
} else if (brw->intel.gen >= 4) {