summaryrefslogtreecommitdiffstats
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.c16
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.h14
-rw-r--r--src/mesa/drivers/dri/i965/intel_screen.c8
3 files changed, 29 insertions, 9 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 0881e489fe2..51203726438 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -234,8 +234,8 @@ intel_glFlush(struct gl_context *ctx)
intel_batchbuffer_flush(brw);
intel_flush_front(ctx);
- if (brw_is_front_buffer_drawing(ctx->DrawBuffer))
- brw->need_throttle = true;
+
+ brw->need_flush_throttle = true;
}
static void
@@ -1245,12 +1245,20 @@ intel_prepare_render(struct brw_context *brw)
* the swap, and getting our hands on that doesn't seem worth it,
* so we just us the first batch we emitted after the last swap.
*/
- if (brw->need_throttle && brw->first_post_swapbuffers_batch) {
+ if (brw->need_swap_throttle && brw->first_post_swapbuffers_batch) {
if (!brw->disable_throttling)
drm_intel_bo_wait_rendering(brw->first_post_swapbuffers_batch);
drm_intel_bo_unreference(brw->first_post_swapbuffers_batch);
brw->first_post_swapbuffers_batch = NULL;
- brw->need_throttle = false;
+ brw->need_swap_throttle = false;
+ /* Throttling here is more precise than the throttle ioctl, so skip it */
+ brw->need_flush_throttle = false;
+ }
+
+ if (brw->need_flush_throttle) {
+ __DRIscreen *psp = brw->intelScreen->driScrnPriv;
+ drmCommandNone(psp->fd, DRM_I915_GEM_THROTTLE);
+ brw->need_flush_throttle = false;
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 682fbe97db0..eebd7cec72e 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1031,7 +1031,19 @@ struct brw_context
/** Framerate throttling: @{ */
drm_intel_bo *first_post_swapbuffers_batch;
- bool need_throttle;
+
+ /* Limit the number of outstanding SwapBuffers by waiting for an earlier
+ * frame of rendering to complete. This gives a very precise cap to the
+ * latency between input and output such that rendering never gets more
+ * than a frame behind the user. (With the caveat that we technically are
+ * not using the SwapBuffers itself as a barrier but the first batch
+ * submitted afterwards, which may be immediately prior to the next
+ * SwapBuffers.)
+ */
+ bool need_swap_throttle;
+
+ /** General throttling, not caught by throttling between SwapBuffers */
+ bool need_flush_throttle;
/** @} */
GLuint stats_wm;
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index cea7ddfe67a..3640b675471 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -174,10 +174,10 @@ intel_dri2_flush_with_flags(__DRIcontext *cPriv,
if (flags & __DRI2_FLUSH_DRAWABLE)
intel_resolve_for_dri2_flush(brw, dPriv);
- if (reason == __DRI2_THROTTLE_SWAPBUFFER ||
- reason == __DRI2_THROTTLE_FLUSHFRONT) {
- brw->need_throttle = true;
- }
+ if (reason == __DRI2_THROTTLE_SWAPBUFFER)
+ brw->need_swap_throttle = true;
+ if (reason == __DRI2_THROTTLE_FLUSHFRONT)
+ brw->need_flush_throttle = true;
intel_batchbuffer_flush(brw);