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-rw-r--r--src/gallium/drivers/radeon/r600_texture.c8
-rw-r--r--src/gallium/winsys/amdgpu/drm/amdgpu_surface.c7
2 files changed, 11 insertions, 4 deletions
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 77e9becda6a..d811a77ca86 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -2639,10 +2639,6 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
if (rctx->render_cond)
return;
- /* TODO: fix CMASK and DCC fast clear */
- if (rctx->chip_class >= GFX9)
- return;
-
for (i = 0; i < fb->nr_cbufs; i++) {
struct r600_texture *tex;
unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
@@ -2710,6 +2706,10 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
uint32_t reset_value;
bool clear_words_needed;
+ /* TODO: fix DCC clear */
+ if (rctx->chip_class >= GFX9)
+ continue;
+
if (rctx->screen->debug_flags & DBG_NO_DCC_CLEAR)
continue;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 1e63d646710..4d532e397d0 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -655,6 +655,13 @@ static int gfx9_compute_miptree(struct amdgpu_winsys *ws,
surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
out.mipChainPitch - 1;
+
+ /* CMASK fast clear uses these even if FMASK isn't allocated.
+ * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
+ */
+ surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
+ surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
+
surf->u.gfx9.surf_slice_size = out.sliceSize;
surf->u.gfx9.surf_pitch = out.pitch;
surf->u.gfx9.surf_height = out.height;