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-rw-r--r--src/amd/vulkan/radv_cmd_buffer.c19
-rw-r--r--src/amd/vulkan/radv_device.c21
-rw-r--r--src/amd/vulkan/radv_image.c7
-rw-r--r--src/amd/vulkan/radv_meta_clear.c2
-rw-r--r--src/amd/vulkan/radv_private.h2
5 files changed, 11 insertions, 40 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 58746d3f9b8..a9be8974271 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -926,12 +926,12 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
VkImageLayout layout)
{
uint32_t db_z_info = ds->db_z_info;
+ uint32_t db_stencil_info = ds->db_stencil_info;
- if (!radv_layout_has_htile(image, layout))
+ if (!radv_layout_has_htile(image, layout)) {
db_z_info &= C_028040_TILE_SURFACE_ENABLE;
-
- if (!radv_layout_can_expclear(image, layout))
- db_z_info &= C_028040_ALLOW_EXPCLEAR & C_028044_ALLOW_EXPCLEAR;
+ db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
+ }
radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
@@ -939,7 +939,7 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
- radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
+ radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
@@ -3003,13 +3003,8 @@ static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffe
radv_layout_has_htile(image, dst_layout)) {
/* TODO: merge with the clear if applicable */
radv_initialize_htile(cmd_buffer, image, range);
- } else if (!radv_layout_has_htile(image, src_layout) &&
- radv_layout_has_htile(image, dst_layout)) {
- radv_initialize_htile(cmd_buffer, image, range);
- } else if ((radv_layout_has_htile(image, src_layout) &&
- !radv_layout_has_htile(image, dst_layout)) ||
- (radv_layout_is_htile_compressed(image, src_layout) &&
- !radv_layout_is_htile_compressed(image, dst_layout))) {
+ } else if (radv_layout_is_htile_compressed(image, src_layout) &&
+ !radv_layout_is_htile_compressed(image, dst_layout)) {
VkImageSubresourceRange local_range = *range;
local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
local_range.baseMipLevel = 0;
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 921b8e48f5b..2d89e8635e7 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2846,24 +2846,9 @@ radv_initialise_ds_surface(struct radv_device *device,
}
if (iview->image->surface.htile_size && !level) {
- ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
- S_028040_ALLOW_EXPCLEAR(1);
-
- if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
- /* Workaround: For a not yet understood reason, the
- * combination of MSAA, fast stencil clear and stencil
- * decompress messes with subsequent stencil buffer
- * uses. Problem was reproduced on Verde, Bonaire,
- * Tonga, and Carrizo.
- *
- * Disabling EXPCLEAR works around the problem.
- *
- * Check piglit's arb_texture_multisample-stencil-clear
- * test if you want to try changing this.
- */
- if (iview->image->info.samples <= 1)
- ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
- } else
+ ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
+
+ if (!(iview->image->surface.flags & RADEON_SURF_SBUFFER))
/* Use all of the htile_buffer for depth if there's no stencil. */
ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index e1e9d9c86b8..0a36be0822d 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -783,13 +783,6 @@ bool radv_layout_is_htile_compressed(const struct radv_image *image,
return layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL;
}
-bool radv_layout_can_expclear(const struct radv_image *image,
- VkImageLayout layout)
-{
- return (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
- layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL);
-}
-
bool radv_layout_can_fast_clear(const struct radv_image *image,
VkImageLayout layout,
unsigned queue_mask)
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 57b812d2b14..18b4ca9ba2b 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -551,7 +551,7 @@ static bool depth_view_can_fast_clear(const struct radv_image_view *iview,
if (iview->image->surface.htile_size &&
iview->base_mip == 0 &&
iview->base_layer == 0 &&
- radv_layout_can_expclear(iview->image, layout) &&
+ radv_layout_is_htile_compressed(iview->image, layout) &&
!radv_image_extent_compare(iview->image, &iview->extent))
return true;
return false;
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index b78d22183f0..6c4027bbdb8 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1190,8 +1190,6 @@ bool radv_layout_has_htile(const struct radv_image *image,
VkImageLayout layout);
bool radv_layout_is_htile_compressed(const struct radv_image *image,
VkImageLayout layout);
-bool radv_layout_can_expclear(const struct radv_image *image,
- VkImageLayout layout);
bool radv_layout_can_fast_clear(const struct radv_image *image,
VkImageLayout layout,
unsigned queue_mask);
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-12 05:59:39 +0000