diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/v3d/v3d_simulator_wrapper.cpp | 5 | ||||
| -rw-r--r-- | src/gallium/drivers/v3d/v3d_simulator_wrapper.h | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/v3d/v3dx_simulator.c | 33 |
3 files changed, 39 insertions, 0 deletions
diff --git a/src/gallium/drivers/v3d/v3d_simulator_wrapper.cpp b/src/gallium/drivers/v3d/v3d_simulator_wrapper.cpp index 7b04ded2b53..15db767d534 100644 --- a/src/gallium/drivers/v3d/v3d_simulator_wrapper.cpp +++ b/src/gallium/drivers/v3d/v3d_simulator_wrapper.cpp @@ -83,6 +83,11 @@ int v3d_hw_get_version(struct v3d_hw *hw) return ident->tech_version * 10 + ident->revision; } +void +v3d_hw_set_isr(struct v3d_hw *hw, void (*isr)(uint32_t status)) +{ + hw->set_isr(isr); } +} #endif /* USE_V3D_SIMULATOR */ diff --git a/src/gallium/drivers/v3d/v3d_simulator_wrapper.h b/src/gallium/drivers/v3d/v3d_simulator_wrapper.h index 8b5dca15ed9..b20ea2484b4 100644 --- a/src/gallium/drivers/v3d/v3d_simulator_wrapper.h +++ b/src/gallium/drivers/v3d/v3d_simulator_wrapper.h @@ -38,6 +38,7 @@ uint32_t v3d_hw_read_reg(struct v3d_hw *hw, uint32_t reg); void v3d_hw_write_reg(struct v3d_hw *hw, uint32_t reg, uint32_t val); void v3d_hw_tick(struct v3d_hw *hw); int v3d_hw_get_version(struct v3d_hw *hw); +void v3d_hw_set_isr(struct v3d_hw *hw, void (*isr)(uint32_t status)); #ifdef __cplusplus } diff --git a/src/gallium/drivers/v3d/v3dx_simulator.c b/src/gallium/drivers/v3d/v3dx_simulator.c index 940b8f2ce32..e6db838c0de 100644 --- a/src/gallium/drivers/v3d/v3dx_simulator.c +++ b/src/gallium/drivers/v3d/v3dx_simulator.c @@ -157,6 +157,32 @@ v3dX(simulator_get_param_ioctl)(struct v3d_hw *v3d, abort(); } +static struct v3d_hw *v3d_isr_hw; + +static void +v3d_isr(uint32_t hub_status) +{ + struct v3d_hw *v3d = v3d_isr_hw; + + /* Check the per-core bits */ + if (hub_status & (1 << 0)) { + uint32_t core_status = V3D_READ(V3D_CTL_0_INT_STS); + + if (core_status & V3D_CTL_0_INT_STS_INT_GMPV_SET) { + fprintf(stderr, "GMP violation at 0x%08x\n", + V3D_READ(V3D_GMP_0_VIO_ADDR)); + abort(); + } else { + fprintf(stderr, + "Unexpected ISR with core status 0x%08x\n", + core_status); + } + abort(); + } + + return; +} + void v3dX(simulator_init_regs)(struct v3d_hw *v3d) { @@ -171,6 +197,13 @@ v3dX(simulator_init_regs)(struct v3d_hw *v3d) */ V3D_WRITE(V3D_CTL_0_MISCCFG, V3D_CTL_1_MISCCFG_OVRTMUOUT_SET); #endif + + uint32_t core_interrupts = V3D_CTL_0_INT_STS_INT_GMPV_SET; + V3D_WRITE(V3D_CTL_0_INT_MSK_SET, ~core_interrupts); + V3D_WRITE(V3D_CTL_0_INT_MSK_CLR, core_interrupts); + + v3d_isr_hw = v3d; + v3d_hw_set_isr(v3d, v3d_isr); } void |