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Diffstat (limited to 'src')
-rw-r--r-- | src/intel/vulkan/genX_state.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index 75bcd96d78a..42800a2581e 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -157,6 +157,16 @@ genX(init_device_state)(struct anv_device *device) GEN_SAMPLE_POS_16X(sp._16xSample); #endif } + + /* The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in the + * section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer + * Clear." It mentions that the packet overrides GPU state for the clear + * operation and needs to be reset to 0s to clear the overrides. Depending + * on the kernel, we may not get a context with the state for this packet + * zeroed. Do it ourselves just in case. We've observed this to prevent a + * number of GPU hangs on ICL. + */ + anv_batch_emit(&batch, GENX(3DSTATE_WM_HZ_OP), hzp); #endif #if GEN_GEN == 10 |