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-rw-r--r--src/mesa/drivers/dri/i965/Makefile.sources1
-rw-r--r--src/mesa/drivers/dri/i965/brw_defines.h5
-rw-r--r--src/mesa/drivers/dri/i965/brw_state.h1
-rw-r--r--src/mesa/drivers/dri/i965/brw_state_upload.c2
-rw-r--r--src/mesa/drivers/dri/i965/gen8_gs_state.c147
5 files changed, 155 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources
index f47ea6b4d0b..dc30eb371e9 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -149,6 +149,7 @@ i965_FILES = \
gen8_fs_generator.cpp \
gen8_generator.cpp \
gen8_instruction.c \
+ gen8_gs_state.c \
gen8_misc_state.c \
gen8_multisample_state.c \
gen8_sf_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index e2869422f2a..b29d0c44bb8 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1530,6 +1530,11 @@ enum brw_message_target {
# define GEN6_GS_SVBI_POSTINCREMENT_VALUE_MASK INTEL_MASK(25, 16)
# define GEN6_GS_ENABLE (1 << 15)
+/* Gen8+ DW9 */
+# define GEN8_GS_URB_ENTRY_OUTPUT_OFFSET_SHIFT 21
+# define GEN8_GS_URB_OUTPUT_LENGTH_SHIFT 16
+# define GEN8_GS_USER_CLIP_DISTANCE_SHIFT 8
+
# define BRW_GS_EDGE_INDICATOR_0 (1 << 8)
# define BRW_GS_EDGE_INDICATOR_1 (1 << 9)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 40a152f1490..72478bae3d3 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -133,6 +133,7 @@ extern const struct brw_tracked_state gen7_wm_state;
extern const struct brw_tracked_state haswell_cut_index;
extern const struct brw_tracked_state gen8_blend_state;
extern const struct brw_tracked_state gen8_disable_stages;
+extern const struct brw_tracked_state gen8_gs_state;
extern const struct brw_tracked_state gen8_index_buffer;
extern const struct brw_tracked_state gen8_multisample_state;
extern const struct brw_tracked_state gen8_ps_blend;
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 5ecebf5c015..226a9c021e2 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -298,7 +298,7 @@ static const struct brw_tracked_state *gen8_atoms[] =
&gen8_disable_stages,
&gen8_vs_state,
- &gen7_gs_state,
+ &gen8_gs_state,
&gen8_sol_state,
&gen6_clip_state,
&gen8_raster_state,
diff --git a/src/mesa/drivers/dri/i965/gen8_gs_state.c b/src/mesa/drivers/dri/i965/gen8_gs_state.c
new file mode 100644
index 00000000000..c018d7084fb
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/gen8_gs_state.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "brw_context.h"
+#include "brw_state.h"
+#include "brw_defines.h"
+#include "intel_batchbuffer.h"
+
+static void
+gen8_upload_gs_state(struct brw_context *brw)
+{
+ struct gl_context *ctx = &brw->ctx;
+ const struct brw_stage_state *stage_state = &brw->gs.base;
+ /* BRW_NEW_GEOMETRY_PROGRAM */
+ bool active = brw->geometry_program;
+ /* CACHE_NEW_GS_PROG */
+ const struct brw_vec4_prog_data *prog_data = &brw->gs.prog_data->base;
+
+ /* BRW_NEW_GS_BINDING_TABLE */
+ BEGIN_BATCH(2);
+ OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_GS << 16 | (2 - 2));
+ OUT_BATCH(stage_state->bind_bo_offset);
+ ADVANCE_BATCH();
+
+ /* CACHE_NEW_SAMPLER */
+ BEGIN_BATCH(2);
+ OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_GS << 16 | (2 - 2));
+ OUT_BATCH(stage_state->sampler_offset);
+ ADVANCE_BATCH();
+
+ gen8_upload_constant_state(brw, stage_state, active, _3DSTATE_CONSTANT_GS);
+
+ if (active) {
+ int urb_entry_write_offset = 1;
+ uint32_t urb_entry_output_length =
+ ((prog_data->vue_map.num_slots + 1) / 2 - urb_entry_write_offset);
+
+ if (urb_entry_output_length == 0)
+ urb_entry_output_length = 1;
+
+ BEGIN_BATCH(10);
+ OUT_BATCH(_3DSTATE_GS << 16 | (10 - 2));
+ OUT_BATCH(stage_state->prog_offset);
+ OUT_BATCH(0);
+ OUT_BATCH(GEN6_GS_VECTOR_MASK_ENABLE |
+ brw->geometry_program->VerticesIn |
+ ((ALIGN(stage_state->sampler_count, 4)/4) <<
+ GEN6_GS_SAMPLER_COUNT_SHIFT) |
+ ((prog_data->base.binding_table.size_bytes / 4) <<
+ GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
+
+ if (brw->gs.prog_data->base.total_scratch) {
+ OUT_RELOC64(stage_state->scratch_bo,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ ffs(brw->gs.prog_data->base.total_scratch) - 11);
+ WARN_ONCE(true,
+ "May need to implement a temporary workaround: GS Number of "
+ "URB Entries must be less than or equal to the GS Maximum "
+ "Number of Threads.\n");
+ } else {
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ }
+
+ /* DW6 */
+ OUT_BATCH(((brw->gs.prog_data->output_vertex_size_hwords * 2 - 1) <<
+ GEN7_GS_OUTPUT_VERTEX_SIZE_SHIFT) |
+ (brw->gs.prog_data->output_topology <<
+ GEN7_GS_OUTPUT_TOPOLOGY_SHIFT) |
+ (prog_data->urb_read_length <<
+ GEN6_GS_URB_READ_LENGTH_SHIFT) |
+ (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT) |
+ (prog_data->dispatch_grf_start_reg <<
+ GEN6_GS_DISPATCH_START_GRF_SHIFT));
+
+ /* DW7 */
+ OUT_BATCH(((brw->max_gs_threads / 2 - 1) << HSW_GS_MAX_THREADS_SHIFT) |
+ (brw->gs.prog_data->control_data_header_size_hwords <<
+ GEN7_GS_CONTROL_DATA_HEADER_SIZE_SHIFT) |
+ (brw->gs.prog_data->dual_instanced_dispatch ?
+ GEN7_GS_DISPATCH_MODE_DUAL_INSTANCE :
+ GEN7_GS_DISPATCH_MODE_DUAL_OBJECT) |
+ GEN6_GS_STATISTICS_ENABLE |
+ (brw->gs.prog_data->include_primitive_id ?
+ GEN7_GS_INCLUDE_PRIMITIVE_ID : 0) |
+ GEN7_GS_REORDER_TRAILING |
+ GEN7_GS_ENABLE);
+
+ /* DW8 */
+ OUT_BATCH(brw->gs.prog_data->control_data_format <<
+ HSW_GS_CONTROL_DATA_FORMAT_SHIFT);
+
+ /* DW9 / _NEW_TRANSFORM */
+ OUT_BATCH((ctx->Transform.ClipPlanesEnabled <<
+ GEN8_GS_USER_CLIP_DISTANCE_SHIFT) |
+ (urb_entry_output_length << GEN8_GS_URB_OUTPUT_LENGTH_SHIFT) |
+ (urb_entry_write_offset <<
+ GEN8_GS_URB_ENTRY_OUTPUT_OFFSET_SHIFT));
+ ADVANCE_BATCH();
+ } else {
+ BEGIN_BATCH(10);
+ OUT_BATCH(_3DSTATE_GS << 16 | (10 - 2));
+ OUT_BATCH(0); /* prog_bo */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* scratch space base offset */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(GEN6_GS_STATISTICS_ENABLE);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+ }
+}
+
+const struct brw_tracked_state gen8_gs_state = {
+ .dirty = {
+ .mesa = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
+ .brw = (BRW_NEW_CONTEXT |
+ BRW_NEW_GEOMETRY_PROGRAM |
+ BRW_NEW_GS_BINDING_TABLE |
+ BRW_NEW_BATCH |
+ BRW_NEW_PUSH_CONSTANT_ALLOCATION),
+ .cache = CACHE_NEW_GS_PROG | CACHE_NEW_SAMPLER
+ },
+ .emit = gen8_upload_gs_state,
+};
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 17:59:36 +0000