diff options
Diffstat (limited to 'src/vulkan')
| -rw-r--r-- | src/vulkan/Makefile.am | 1 | ||||
| -rw-r--r-- | src/vulkan/anv_compiler.cpp | 3 | ||||
| -rw-r--r-- | src/vulkan/anv_nir.h | 2 | ||||
| -rw-r--r-- | src/vulkan/anv_nir_apply_pipeline_layout.c | 217 |
4 files changed, 223 insertions, 0 deletions
diff --git a/src/vulkan/Makefile.am b/src/vulkan/Makefile.am index a691329065c..aeed78ae840 100644 --- a/src/vulkan/Makefile.am +++ b/src/vulkan/Makefile.am @@ -70,6 +70,7 @@ VULKAN_SOURCES = \ anv_intel.c \ anv_meta.c \ anv_nir_apply_dynamic_offsets.c \ + anv_nir_apply_pipeline_layout.c \ anv_pipeline.c \ anv_private.h \ anv_query.c \ diff --git a/src/vulkan/anv_compiler.cpp b/src/vulkan/anv_compiler.cpp index bf931fe886f..34023a7369f 100644 --- a/src/vulkan/anv_compiler.cpp +++ b/src/vulkan/anv_compiler.cpp @@ -285,6 +285,7 @@ really_do_vs_prog(struct brw_context *brw, create_params_array(pipeline, vs, &prog_data->base.base); anv_nir_apply_dynamic_offsets(pipeline, vs->Program->nir, &prog_data->base.base); + anv_nir_apply_pipeline_layout(vs->Program->nir, pipeline->layout); GLbitfield64 outputs_written = vp->program.Base.OutputsWritten; prog_data->inputs_read = vp->program.Base.InputsRead; @@ -571,6 +572,7 @@ really_do_wm_prog(struct brw_context *brw, create_params_array(pipeline, fs, &prog_data->base); anv_nir_apply_dynamic_offsets(pipeline, fs->Program->nir, &prog_data->base); + anv_nir_apply_pipeline_layout(fs->Program->nir, pipeline->layout); prog_data->barycentric_interp_modes = brw_compute_barycentric_interp_modes(brw->intelScreen->devinfo, @@ -888,6 +890,7 @@ brw_codegen_cs_prog(struct brw_context *brw, create_params_array(pipeline, cs, &prog_data->base); anv_nir_apply_dynamic_offsets(pipeline, cs->Program->nir, &prog_data->base); + anv_nir_apply_pipeline_layout(cs->Program->nir, pipeline->layout); program = brw_cs_emit(brw, mem_ctx, key, prog_data, &cp->program, prog, -1, &program_size); diff --git a/src/vulkan/anv_nir.h b/src/vulkan/anv_nir.h index 1fd3484e059..af95e3a8849 100644 --- a/src/vulkan/anv_nir.h +++ b/src/vulkan/anv_nir.h @@ -40,6 +40,8 @@ anv_vk_shader_stage_for_mesa_stage(gl_shader_stage stage) void anv_nir_apply_dynamic_offsets(struct anv_pipeline *pipeline, nir_shader *shader, struct brw_stage_prog_data *prog_data); +bool anv_nir_apply_pipeline_layout(nir_shader *shader, + const struct anv_pipeline_layout *layout); #ifdef __cplusplus } diff --git a/src/vulkan/anv_nir_apply_pipeline_layout.c b/src/vulkan/anv_nir_apply_pipeline_layout.c new file mode 100644 index 00000000000..dea2dee3b32 --- /dev/null +++ b/src/vulkan/anv_nir_apply_pipeline_layout.c @@ -0,0 +1,217 @@ +/* + * Copyright © 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include "anv_nir.h" +#include "glsl/nir/nir_builder.h" + +struct apply_pipeline_layout_state { + nir_shader *shader; + nir_builder builder; + + VkShaderStage stage; + const struct anv_pipeline_layout *layout; + + bool progress; +}; + +static nir_intrinsic_op +lowered_op(nir_intrinsic_op op) +{ + switch (op) { + case nir_intrinsic_load_ubo_vk: + return nir_intrinsic_load_ubo; + case nir_intrinsic_load_ubo_vk_indirect: + return nir_intrinsic_load_ubo_indirect; + case nir_intrinsic_load_ssbo_vk: + return nir_intrinsic_load_ssbo; + case nir_intrinsic_load_ssbo_vk_indirect: + return nir_intrinsic_load_ssbo_indirect; + case nir_intrinsic_store_ssbo_vk: + return nir_intrinsic_store_ssbo; + case nir_intrinsic_store_ssbo_vk_indirect: + return nir_intrinsic_store_ssbo_indirect; + default: + unreachable("Invalid intrinsic for lowering"); + } +} + +static uint32_t +get_surface_index(unsigned set, unsigned binding, + struct apply_pipeline_layout_state *state) +{ + assert(set < state->layout->num_sets); + struct anv_descriptor_set_layout *set_layout = + state->layout->set[set].layout; + + assert(binding < set_layout->binding_count); + + assert(set_layout->binding[binding].stage[state->stage].surface_index >= 0); + + uint32_t surface_index = + state->layout->set[set].stage[state->stage].surface_start + + set_layout->binding[binding].stage[state->stage].surface_index; + + assert(surface_index < state->layout->stage[state->stage].surface_count); + + return surface_index; +} + +static bool +try_lower_intrinsic(nir_intrinsic_instr *intrin, + struct apply_pipeline_layout_state *state) +{ + nir_builder *b = &state->builder; + + int block_idx_src; + switch (intrin->intrinsic) { + case nir_intrinsic_load_ubo_vk: + case nir_intrinsic_load_ubo_vk_indirect: + case nir_intrinsic_load_ssbo_vk: + case nir_intrinsic_load_ssbo_vk_indirect: + block_idx_src = 0; + break; + case nir_intrinsic_store_ssbo_vk: + case nir_intrinsic_store_ssbo_vk_indirect: + block_idx_src = 1; + break; + default: + return false; + } + + b->cursor = nir_before_instr(&intrin->instr); + + uint32_t set = intrin->const_index[0]; + uint32_t binding = intrin->const_index[1]; + + uint32_t surface_index = get_surface_index(set, binding, state); + + nir_const_value *const_block_idx = + nir_src_as_const_value(intrin->src[block_idx_src]); + + nir_ssa_def *block_index; + if (const_block_idx) { + block_index = nir_imm_int(b, surface_index + const_block_idx->u[0]); + } else { + block_index = nir_iadd(b, nir_imm_int(b, surface_index), + nir_ssa_for_src(b, intrin->src[block_idx_src], 1)); + } + + nir_instr_rewrite_src(&intrin->instr, &intrin->src[block_idx_src], + nir_src_for_ssa(block_index)); + + intrin->intrinsic = lowered_op(intrin->intrinsic); + /* Shift the offset indices down */ + intrin->const_index[0] = intrin->const_index[2]; + intrin->const_index[1] = intrin->const_index[3]; + + return true; +} + +static void +lower_tex(nir_tex_instr *tex, struct apply_pipeline_layout_state *state) +{ + /* No one should have come by and lowered it already */ + assert(tex->sampler); + + unsigned set = tex->sampler->var->data.descriptor_set; + unsigned binding = tex->sampler->var->data.binding; + + tex->sampler_index = get_surface_index(set, binding, state); + + if (tex->sampler->deref.child) { + assert(tex->sampler->deref.child->deref_type == nir_deref_type_array); + nir_deref_array *deref_array = + nir_deref_as_array(tex->sampler->deref.child); + + tex->sampler_index += deref_array->base_offset; + + if (deref_array->deref_array_type == nir_deref_array_type_indirect) { + nir_tex_src *new_srcs = rzalloc_array(tex, nir_tex_src, + tex->num_srcs + 1); + + for (unsigned i = 0; i < tex->num_srcs; i++) { + new_srcs[i].src_type = tex->src[i].src_type; + nir_instr_move_src(&tex->instr, &new_srcs[i].src, &tex->src[i].src); + } + + ralloc_free(tex->src); + tex->src = new_srcs; + + /* Now we can go ahead and move the source over to being a + * first-class texture source. + */ + tex->src[tex->num_srcs].src_type = nir_tex_src_sampler_offset; + tex->num_srcs++; + nir_instr_move_src(&tex->instr, &tex->src[tex->num_srcs - 1].src, + &deref_array->indirect); + } + } + + tex->sampler = NULL; +} + +static bool +apply_pipeline_layout_block(nir_block *block, void *void_state) +{ + struct apply_pipeline_layout_state *state = void_state; + + nir_foreach_instr_safe(block, instr) { + switch (instr->type) { + case nir_instr_type_intrinsic: + if (try_lower_intrinsic(nir_instr_as_intrinsic(instr), state)) + state->progress = true; + break; + case nir_instr_type_tex: + lower_tex(nir_instr_as_tex(instr), state); + /* All texture instructions need lowering */ + state->progress = true; + break; + default: + continue; + } + } + + return true; +} + +bool +anv_nir_apply_pipeline_layout(nir_shader *shader, + const struct anv_pipeline_layout *layout) +{ + struct apply_pipeline_layout_state state = { + .shader = shader, + .stage = anv_vk_shader_stage_for_mesa_stage(shader->stage), + .layout = layout, + }; + + nir_foreach_overload(shader, overload) { + if (overload->impl) { + nir_builder_init(&state.builder, overload->impl); + nir_foreach_block(overload->impl, apply_pipeline_layout_block, &state); + nir_metadata_preserve(overload->impl, nir_metadata_block_index | + nir_metadata_dominance); + } + } + + return state.progress; +} |