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-rw-r--r--src/vulkan/gen7_pipeline.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/vulkan/gen7_pipeline.c b/src/vulkan/gen7_pipeline.c
index bcfa986769e..7d44c72b1a2 100644
--- a/src/vulkan/gen7_pipeline.c
+++ b/src/vulkan/gen7_pipeline.c
@@ -224,17 +224,12 @@ gen7_emit_ds_state(struct anv_pipeline *pipeline,
return;
}
- bool has_stencil = false; /* enable if subpass has stencil? */
-
struct GEN7_DEPTH_STENCIL_STATE state = {
.DepthTestEnable = info->depthTestEnable,
.DepthBufferWriteEnable = info->depthWriteEnable,
.DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
.DoubleSidedStencilEnable = true,
- /* Is this what we need to do? */
- .StencilBufferWriteEnable = has_stencil,
-
.StencilTestEnable = info->stencilTestEnable,
.StencilFailOp = vk_to_gen_stencil_op[info->front.stencilFailOp],
.StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.stencilPassOp],