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-rw-r--r--src/panfrost/midgard/disassemble.c18
1 files changed, 15 insertions, 3 deletions
diff --git a/src/panfrost/midgard/disassemble.c b/src/panfrost/midgard/disassemble.c
index 1cebd7814a6..5a1b67a8ff9 100644
--- a/src/panfrost/midgard/disassemble.c
+++ b/src/panfrost/midgard/disassemble.c
@@ -354,9 +354,21 @@ print_vector_src(unsigned src_binary,
print_reg(reg, bits);
//swizzle
- if (bits == 16)
- print_swizzle_vec8(src->swizzle, src->rep_high, src->rep_low);
- else if (bits == 8)
+ if (bits == 16) {
+ /* When the mode of the instruction is itself 16-bit,
+ * rep_low/high work more or less as expected. But if the mode
+ * is 32-bit and we're stepping down, you only have vec4 and
+ * the meaning shifts to rep_low as higher-half and rep_high is
+ * never seen. TODO: are other modes similar? */
+
+ if (mode == midgard_reg_mode_32) {
+ printf(".");
+ print_swizzle_helper(src->swizzle, src->rep_low);
+ assert(!src->rep_high);
+ } else {
+ print_swizzle_vec8(src->swizzle, src->rep_high, src->rep_low);
+ }
+ } else if (bits == 8)
print_swizzle_vec16(src->swizzle, src->rep_high, src->rep_low, override);
else if (bits == 32)
print_swizzle_vec4(src->swizzle, src->rep_high, src->rep_low);