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-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_fp.cpp14
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_visitor.cpp13
-rw-r--r--src/mesa/drivers/dri/i965/brw_shader.h1
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4.h1
4 files changed, 15 insertions, 14 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
index 0594948ee06..1ebaa4f2c81 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
@@ -137,8 +137,8 @@ fs_visitor::emit_fragment_program_code()
fs_reg one = fs_reg(this, glsl_type::float_type);
emit(MOV(one, fs_reg(1.0f)));
- for (unsigned int insn = 0; insn < fp->Base.NumInstructions; insn++) {
- const struct prog_instruction *fpi = &fp->Base.Instructions[insn];
+ for (unsigned int insn = 0; insn < prog->NumInstructions; insn++) {
+ const struct prog_instruction *fpi = &prog->Instructions[insn];
base_ir = fpi;
//_mesa_print_instruction(fpi);
@@ -583,7 +583,7 @@ void
fs_visitor::setup_fp_regs()
{
/* PROGRAM_TEMPORARY */
- int num_temp = fp->Base.NumTemporaries;
+ int num_temp = prog->NumTemporaries;
fp_temp_regs = rzalloc_array(mem_ctx, fs_reg, num_temp);
for (int i = 0; i < num_temp; i++)
fp_temp_regs[i] = fs_reg(this, glsl_type::vec4_type);
@@ -591,17 +591,17 @@ fs_visitor::setup_fp_regs()
/* PROGRAM_STATE_VAR etc. */
if (dispatch_width == 8) {
for (unsigned p = 0;
- p < fp->Base.Parameters->NumParameters; p++) {
+ p < prog->Parameters->NumParameters; p++) {
for (unsigned int i = 0; i < 4; i++) {
c->prog_data.param[c->prog_data.nr_params++] =
- &fp->Base.Parameters->ParameterValues[p][i].f;
+ &prog->Parameters->ParameterValues[p][i].f;
}
}
}
fp_input_regs = rzalloc_array(mem_ctx, fs_reg, VARYING_SLOT_MAX);
for (int i = 0; i < VARYING_SLOT_MAX; i++) {
- if (fp->Base.InputsRead & BITFIELD64_BIT(i)) {
+ if (prog->InputsRead & BITFIELD64_BIT(i)) {
/* Make up a dummy instruction to reuse code for emitting
* interpolation.
*/
@@ -687,7 +687,7 @@ fs_visitor::get_fp_dst_reg(const prog_dst_register *dst)
fs_reg
fs_visitor::get_fp_src_reg(const prog_src_register *src)
{
- struct gl_program_parameter_list *plist = fp->Base.Parameters;
+ struct gl_program_parameter_list *plist = prog->Parameters;
fs_reg result;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index e659203dd58..ca265e769b7 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1406,7 +1406,7 @@ fs_visitor::rescale_texcoord(ir_texture *ir, fs_reg coordinate,
(brw->gen < 6 ||
(brw->gen >= 6 && (c->key.tex.gl_clamp_mask[0] & (1 << sampler) ||
c->key.tex.gl_clamp_mask[1] & (1 << sampler))))) {
- struct gl_program_parameter_list *params = fp->Base.Parameters;
+ struct gl_program_parameter_list *params = prog->Parameters;
int tokens[STATE_LENGTH] = {
STATE_INTERNAL,
STATE_TEXRECT_SCALE,
@@ -1426,9 +1426,9 @@ fs_visitor::rescale_texcoord(ir_texture *ir, fs_reg coordinate,
GLuint index = _mesa_add_state_reference(params,
(gl_state_index *)tokens);
c->prog_data.param[c->prog_data.nr_params++] =
- &fp->Base.Parameters->ParameterValues[index][0].f;
+ &prog->Parameters->ParameterValues[index][0].f;
c->prog_data.param[c->prog_data.nr_params++] =
- &fp->Base.Parameters->ParameterValues[index][1].f;
+ &prog->Parameters->ParameterValues[index][1].f;
}
/* The 965 requires the EU to do the normalization of GL rectangle
@@ -1497,12 +1497,12 @@ fs_visitor::visit(ir_texture *ir)
fs_inst *inst = NULL;
int sampler =
- _mesa_get_sampler_uniform_value(ir->sampler, shader_prog, &fp->Base);
+ _mesa_get_sampler_uniform_value(ir->sampler, shader_prog, prog);
/* FINISHME: We're failing to recompile our programs when the sampler is
* updated. This only matters for the texture rectangle scale parameters
* (pre-gen6, or gen6+ with GL_CLAMP).
*/
- int texunit = fp->Base.SamplerUnits[sampler];
+ int texunit = prog->SamplerUnits[sampler];
if (ir->op == ir_tg4) {
/* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
@@ -2520,7 +2520,7 @@ fs_visitor::emit_fb_writes()
fail("Missing support for simd16 depth writes on gen6\n");
}
- if (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
+ if (prog->OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
/* Hand over gl_FragDepth. */
assert(this->frag_depth.file != BAD_FILE);
emit(MOV(fs_reg(MRF, nr), this->frag_depth));
@@ -2669,6 +2669,7 @@ fs_visitor::fs_visitor(struct brw_context *brw,
this->brw = brw;
this->fp = fp;
this->shader_prog = shader_prog;
+ this->prog = &fp->Base;
this->ctx = &brw->ctx;
this->mem_ctx = ralloc_context(NULL);
if (shader_prog)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index 21a0ad66c42..8b2d7a7ad17 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -59,6 +59,7 @@ public:
struct gl_context *ctx;
struct brw_shader *shader;
struct gl_shader_program *shader_prog;
+ struct gl_program *prog;
/** ralloc context for temporary data used during compile */
void *mem_ctx;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 91f1b6442cc..41d91e5c49d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -250,7 +250,6 @@ public:
return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
}
- struct gl_program *prog;
struct brw_vec4_compile *c;
const struct brw_vec4_prog_key *key;
struct brw_vec4_prog_data *prog_data;
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-21 01:34:39 +0000