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-rw-r--r--src/mesa/drivers/dri/i965/brw_bufmgr.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_bufmgr.h7
-rw-r--r--src/mesa/drivers/dri/i965/intel_batchbuffer.c1
3 files changed, 0 insertions, 10 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 83c0286e0da..8ba915b179a 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -320,7 +320,6 @@ retry:
bo = LIST_ENTRY(struct brw_bo, bucket->head.prev, head);
list_del(&bo->head);
alloc_from_cache = true;
- bo->align = 0;
} else {
/* For non-render-target BOs (where we're probably
* going to map it first thing in order to fill it
@@ -381,7 +380,6 @@ retry:
bo->gem_handle = create.handle;
bo->bufmgr = bufmgr;
- bo->align = 0;
bo->tiling_mode = I915_TILING_NONE;
bo->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 65e76b27d1b..68f5e0c2c85 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -56,13 +56,6 @@ struct brw_bo {
*/
uint64_t size;
- /**
- * Alignment requirement for object
- *
- * Used for GTT mapping & pinning the object.
- */
- uint64_t align;
-
/** Buffer manager context associated with this buffer object */
struct brw_bufmgr *bufmgr;
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 9147ff82939..ebc02ff3897 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -170,7 +170,6 @@ add_exec_bo(struct intel_batchbuffer *batch, struct brw_bo *bo)
batch->validation_list[batch->exec_count] =
(struct drm_i915_gem_exec_object2) {
.handle = bo->gem_handle,
- .alignment = bo->align,
.offset = bo->gtt_offset,
.flags = bo->kflags,
};