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-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp.c10
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.h4
-rw-r--r--src/mesa/drivers/dri/i965/brw_meta_util.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_surface_formats.c20
-rw-r--r--src/mesa/drivers/dri/i965/brw_tex_layout.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_surface_state.c10
-rw-r--r--src/mesa/drivers/dri/i965/intel_fbo.c2
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.c4
-rw-r--r--src/mesa/drivers/dri/i965/intel_tex.c2
9 files changed, 28 insertions, 28 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 56b866438c3..111c6712f98 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -243,8 +243,8 @@ brw_blorp_to_isl_format(struct brw_context *brw, mesa_format format,
return ISL_FORMAT_R16_UNORM;
default: {
if (is_render_target) {
- assert(brw->format_supported_as_render_target[format]);
- return brw->render_target_format[format];
+ assert(brw->mesa_format_supports_render[format]);
+ return brw->mesa_to_isl_render_format[format];
} else {
return brw_isl_format_for_mesa_format(format);
}
@@ -607,7 +607,7 @@ brw_blorp_copytexsubimage(struct brw_context *brw,
_mesa_get_format_base_format(dst_mt->format) == GL_DEPTH_STENCIL)
return false;
- if (!brw->format_supported_as_render_target[dst_image->TexFormat])
+ if (!brw->mesa_format_supports_render[dst_image->TexFormat])
return false;
/* Source clipping shouldn't be necessary, since copytexsubimage (in
@@ -845,7 +845,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
struct blorp_batch batch;
blorp_batch_init(&brw->blorp, &batch, brw, 0);
blorp_fast_clear(&batch, &surf,
- brw->render_target_format[format],
+ brw->mesa_to_isl_render_format[format],
level, logical_layer, num_layers,
x0, y0, x1, y1);
blorp_batch_finish(&batch);
@@ -877,7 +877,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
struct blorp_batch batch;
blorp_batch_init(&brw->blorp, &batch, brw, 0);
blorp_clear(&batch, &surf,
- brw->render_target_format[format],
+ brw->mesa_to_isl_render_format[format],
ISL_SWIZZLE_IDENTITY,
level, irb_logical_mt_layer(irb), num_layers,
x0, y0, x1, y1,
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 0e300c6c2a1..0336914db84 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1170,8 +1170,8 @@ struct brw_context
const struct brw_tracked_state render_atoms[76];
const struct brw_tracked_state compute_atoms[11];
- enum isl_format render_target_format[MESA_FORMAT_COUNT];
- bool format_supported_as_render_target[MESA_FORMAT_COUNT];
+ enum isl_format mesa_to_isl_render_format[MESA_FORMAT_COUNT];
+ bool mesa_format_supports_render[MESA_FORMAT_COUNT];
/* PrimitiveRestart */
struct {
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c b/src/mesa/drivers/dri/i965/brw_meta_util.c
index 24160796bdf..575f437750b 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
@@ -289,7 +289,7 @@ brw_is_color_fast_clear_compatible(struct brw_context *brw,
*/
if (brw->gen >= 9 &&
brw_isl_format_for_mesa_format(mt->format) !=
- brw->render_target_format[mt->format])
+ brw->mesa_to_isl_render_format[mt->format])
return false;
/* Gen9 doesn't support fast clear on single-sampled SRGB buffers. When
diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c b/src/mesa/drivers/dri/i965/brw_surface_formats.c
index f878317e923..c33cafa8365 100644
--- a/src/mesa/drivers/dri/i965/brw_surface_formats.c
+++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c
@@ -301,21 +301,21 @@ brw_init_surface_formats(struct brw_context *brw)
*/
if (isl_format_supports_rendering(devinfo, render) &&
(isl_format_supports_alpha_blending(devinfo, render) || is_integer)) {
- brw->render_target_format[format] = render;
- brw->format_supported_as_render_target[format] = true;
+ brw->mesa_to_isl_render_format[format] = render;
+ brw->mesa_format_supports_render[format] = true;
}
}
/* We will check this table for FBO completeness, but the surface format
* table above only covered color rendering.
*/
- brw->format_supported_as_render_target[MESA_FORMAT_Z24_UNORM_S8_UINT] = true;
- brw->format_supported_as_render_target[MESA_FORMAT_Z24_UNORM_X8_UINT] = true;
- brw->format_supported_as_render_target[MESA_FORMAT_S_UINT8] = true;
- brw->format_supported_as_render_target[MESA_FORMAT_Z_FLOAT32] = true;
- brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_S8X24_UINT] = true;
+ brw->mesa_format_supports_render[MESA_FORMAT_Z24_UNORM_S8_UINT] = true;
+ brw->mesa_format_supports_render[MESA_FORMAT_Z24_UNORM_X8_UINT] = true;
+ brw->mesa_format_supports_render[MESA_FORMAT_S_UINT8] = true;
+ brw->mesa_format_supports_render[MESA_FORMAT_Z_FLOAT32] = true;
+ brw->mesa_format_supports_render[MESA_FORMAT_Z32_FLOAT_S8X24_UINT] = true;
if (brw->gen >= 8)
- brw->format_supported_as_render_target[MESA_FORMAT_Z_UNORM16] = true;
+ brw->mesa_format_supports_render[MESA_FORMAT_Z_UNORM16] = true;
/* We remap depth formats to a supported texturing format in
* translate_tex_format().
@@ -367,7 +367,7 @@ brw_init_surface_formats(struct brw_context *brw)
for (int i = 0; i < ARRAY_SIZE(rgbx_formats); i++) {
ctx->TextureFormatSupported[rgbx_formats[i]] = false;
- brw->format_supported_as_render_target[rgbx_formats[i]] = false;
+ brw->mesa_format_supports_render[rgbx_formats[i]] = false;
}
}
@@ -424,7 +424,7 @@ brw_render_target_supported(struct brw_context *brw,
return false;
}
- return brw->format_supported_as_render_target[format];
+ return brw->mesa_format_supports_render[format];
}
enum isl_format
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index fd774f42c83..d06d6547975 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -587,7 +587,7 @@ brw_miptree_choose_tiling(struct brw_context *brw,
* alignment of 4 as often as we can, this shouldn't happen very often.
*/
if (brw->gen == 7 && mt->valign == 2 &&
- brw->format_supported_as_render_target[mt->format]) {
+ brw->mesa_format_supports_render[mt->format]) {
return I915_TILING_X;
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 8f9a5e107d6..3615c1805ec 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -211,7 +211,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
assert(brw_render_target_supported(brw, rb));
mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
- if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
+ if (unlikely(!brw->mesa_format_supports_render[rb_format])) {
_mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
__func__, _mesa_get_format_name(rb_format));
}
@@ -222,7 +222,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
MAX2(irb->mt->num_samples, 1) : 1;
struct isl_view view = {
- .format = brw->render_target_format[rb_format],
+ .format = brw->mesa_to_isl_render_format[rb_format],
.base_level = irb->mt_level - irb->mt->first_level,
.levels = 1,
.base_array_layer = irb->mt_layer / layer_multiplier,
@@ -1020,8 +1020,8 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
surf = brw_state_batch(brw, 6 * 4, 32, &offset);
- format = brw->render_target_format[rb_format];
- if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
+ format = brw->mesa_to_isl_render_format[rb_format];
+ if (unlikely(!brw->mesa_format_supports_render[rb_format])) {
_mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
__func__, _mesa_get_format_name(rb_format));
}
@@ -1180,7 +1180,7 @@ update_renderbuffer_read_surfaces(struct brw_context *brw)
uint32_t *surf_offset = &brw->wm.base.surf_offset[surf_index];
if (irb) {
- const enum isl_format format = brw->render_target_format[
+ const enum isl_format format = brw->mesa_to_isl_render_format[
_mesa_get_render_format(ctx, intel_rb_format(irb))];
assert(isl_format_supports_sampling(&brw->screen->devinfo,
format));
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index e49f6df408d..47c2f45d3f5 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -348,7 +348,7 @@ intel_image_target_renderbuffer_storage(struct gl_context *ctx,
}
/* __DRIimage is opaque to the core so it has to be checked here */
- if (!brw->format_supported_as_render_target[image->format]) {
+ if (!brw->mesa_format_supports_render[image->format]) {
_mesa_error(ctx, GL_INVALID_OPERATION,
"glEGLImageTargetRenderbufferStorage(unsupported image format)");
return;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index fe00d4b55ff..7996ca7cc92 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -204,7 +204,7 @@ intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw,
/* There's no point in using an MCS buffer if the surface isn't in a
* renderable format.
*/
- if (!brw->format_supported_as_render_target[mt->format])
+ if (!brw->mesa_format_supports_render[mt->format])
return false;
if (brw->gen >= 9) {
@@ -3709,7 +3709,7 @@ intel_miptree_get_isl_surf(struct brw_context *brw,
break;
default:
surf->usage = ISL_SURF_USAGE_TEXTURE_BIT;
- if (brw->format_supported_as_render_target[mt->format])
+ if (brw->mesa_format_supports_render[mt->format])
surf->usage = ISL_SURF_USAGE_RENDER_TARGET_BIT;
break;
}
diff --git a/src/mesa/drivers/dri/i965/intel_tex.c b/src/mesa/drivers/dri/i965/intel_tex.c
index 6da666c8845..1751f109f77 100644
--- a/src/mesa/drivers/dri/i965/intel_tex.c
+++ b/src/mesa/drivers/dri/i965/intel_tex.c
@@ -325,7 +325,7 @@ intel_set_texture_storage_for_buffer_object(struct gl_context *ctx,
return false;
}
- if (!brw->format_supported_as_render_target[image->TexFormat]) {
+ if (!brw->mesa_format_supports_render[image->TexFormat]) {
perf_debug("Non-renderable PBO format; fallback to CPU mapping\n");
return false;
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 20:43:43 +0000