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-rw-r--r--src/mesa/drivers/dri/i965/brw_program.c5
-rw-r--r--src/mesa/main/glspirv.c2
-rw-r--r--src/mesa/state_tracker/st_glsl_to_nir.cpp2
3 files changed, 5 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index f5ebd3c3b05..96247f32f0f 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -91,14 +91,15 @@ brw_create_nir(struct brw_context *brw,
nir_remove_dead_variables(nir, nir_var_shader_in | nir_var_shader_out);
nir_lower_returns(nir);
- nir_validate_shader(nir);
+ nir_validate_shader(nir, "after glsl_to_nir or spirv_to_nir and "
+ "return lowering");
NIR_PASS_V(nir, nir_lower_io_to_temporaries,
nir_shader_get_entrypoint(nir), true, false);
} else {
nir = prog_to_nir(prog, options);
NIR_PASS_V(nir, nir_lower_regs_to_ssa); /* turn registers into SSA */
}
- nir_validate_shader(nir);
+ nir_validate_shader(nir, "before brw_preprocess_nir");
nir = brw_preprocess_nir(brw->screen->compiler, nir);
diff --git a/src/mesa/main/glspirv.c b/src/mesa/main/glspirv.c
index 972989055e9..98b7ea77348 100644
--- a/src/mesa/main/glspirv.c
+++ b/src/mesa/main/glspirv.c
@@ -234,7 +234,7 @@ _mesa_spirv_to_nir(struct gl_context *ctx,
ralloc_asprintf(nir, "SPIRV:%s:%d",
_mesa_shader_stage_to_abbrev(nir->info.stage),
prog->Name);
- nir_validate_shader(nir);
+ nir_validate_shader(nir, "after spirv_to_nir");
nir->info.separate_shader = linked_shader->Program->info.separate_shader;
diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 911284401e0..fe85eeb458d 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -721,7 +721,7 @@ st_link_nir(struct gl_context *ctx,
PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER);
if (nir_lower_wpos_ytransform(nir, &wpos_options)) {
- nir_validate_shader(nir);
+ nir_validate_shader(nir, "after nir_lower_wpos_ytransform");
_mesa_add_state_reference(shader->Program->Parameters,
wposTransformState);
}