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-rw-r--r--src/mesa/drivers/dri/i965/brw_compiler.h5
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.cpp41
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.h4
-rw-r--r--src/mesa/drivers/dri/i965/brw_link.cpp2
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp2
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_iz.cpp9
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_state.c3
-rw-r--r--src/mesa/drivers/dri/i965/gen7_wm_state.c13
-rw-r--r--src/mesa/drivers/dri/i965/gen8_gs_state.c2
-rw-r--r--src/mesa/drivers/dri/i965/gen8_ps_state.c9
-rw-r--r--src/mesa/drivers/dri/i965/intel_extensions.c3
-rw-r--r--src/mesa/program/ir_to_mesa.cpp4
-rw-r--r--src/mesa/state_tracker/st_atom_shader.c9
-rw-r--r--src/mesa/state_tracker/st_glsl_to_tgsi.cpp7
-rw-r--r--src/mesa/state_tracker/st_program.c24
-rw-r--r--src/mesa/state_tracker/st_program.h1
16 files changed, 91 insertions, 47 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h b/src/mesa/drivers/dri/i965/brw_compiler.h
index cd28bbb6bbf..fb5740114dc 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.h
+++ b/src/mesa/drivers/dri/i965/brw_compiler.h
@@ -387,6 +387,9 @@ struct brw_wm_prog_data {
bool uses_pos_offset;
bool uses_omask;
bool uses_kill;
+ bool uses_src_depth;
+ bool uses_src_w;
+ bool uses_sample_mask;
bool pulls_bary;
uint32_t prog_offset_16;
@@ -626,6 +629,8 @@ struct brw_gs_prog_data
{
struct brw_vue_prog_data base;
+ unsigned vertices_in;
+
/**
* Size of an output vertex, measured in HWORDS (32 bytes).
*/
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 63d6987d240..7e161e8bb48 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -4790,7 +4790,7 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
case IMM:
switch (inst->src[i].type) {
case BRW_REGISTER_TYPE_F:
- fprintf(file, "%ff", inst->src[i].f);
+ fprintf(file, "%-gf", inst->src[i].f);
break;
case BRW_REGISTER_TYPE_W:
case BRW_REGISTER_TYPE_D:
@@ -4898,10 +4898,12 @@ fs_visitor::get_instruction_generating_reg(fs_inst *start,
}
void
-fs_visitor::setup_payload_gen6()
+fs_visitor::setup_fs_payload_gen6()
{
- bool uses_depth =
- (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
+ assert(stage == MESA_SHADER_FRAGMENT);
+ brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
+ brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
+
unsigned barycentric_interp_modes =
(stage == MESA_SHADER_FRAGMENT) ?
((brw_wm_prog_data*) this->prog_data)->barycentric_interp_modes : 0;
@@ -4930,7 +4932,9 @@ fs_visitor::setup_payload_gen6()
}
/* R27: interpolated depth if uses source depth */
- if (uses_depth) {
+ prog_data->uses_src_depth =
+ (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
+ if (prog_data->uses_src_depth) {
payload.source_depth_reg = payload.num_regs;
payload.num_regs++;
if (dispatch_width == 16) {
@@ -4938,8 +4942,11 @@ fs_visitor::setup_payload_gen6()
payload.num_regs++;
}
}
+
/* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
- if (uses_depth) {
+ prog_data->uses_src_w =
+ (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
+ if (prog_data->uses_src_w) {
payload.source_w_reg = payload.num_regs;
payload.num_regs++;
if (dispatch_width == 16) {
@@ -4948,19 +4955,17 @@ fs_visitor::setup_payload_gen6()
}
}
- if (stage == MESA_SHADER_FRAGMENT) {
- brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
- brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
- prog_data->uses_pos_offset = key->compute_pos_offset;
- /* R31: MSAA position offsets. */
- if (prog_data->uses_pos_offset) {
- payload.sample_pos_reg = payload.num_regs;
- payload.num_regs++;
- }
+ prog_data->uses_pos_offset = key->compute_pos_offset;
+ /* R31: MSAA position offsets. */
+ if (prog_data->uses_pos_offset) {
+ payload.sample_pos_reg = payload.num_regs;
+ payload.num_regs++;
}
/* R32: MSAA input coverage mask */
- if (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN) {
+ prog_data->uses_sample_mask =
+ (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN) != 0;
+ if (prog_data->uses_sample_mask) {
assert(devinfo->gen >= 7);
payload.sample_mask_in_reg = payload.num_regs;
payload.num_regs++;
@@ -5397,9 +5402,9 @@ fs_visitor::run_fs(bool do_rep_send)
assert(stage == MESA_SHADER_FRAGMENT);
if (devinfo->gen >= 6)
- setup_payload_gen6();
+ setup_fs_payload_gen6();
else
- setup_payload_gen4();
+ setup_fs_payload_gen4();
if (0) {
emit_dummy_fs();
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index ccdf9433798..89fbbfc90e4 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -115,8 +115,8 @@ public:
bool run_cs();
void optimize();
void allocate_registers();
- void setup_payload_gen4();
- void setup_payload_gen6();
+ void setup_fs_payload_gen4();
+ void setup_fs_payload_gen6();
void setup_vs_payload();
void setup_gs_payload();
void setup_cs_payload();
diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp
index f48c6fe12a1..b512f8b6ee1 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -27,6 +27,7 @@
#include "brw_nir.h"
#include "brw_program.h"
#include "compiler/glsl/ir_optimization.h"
+#include "compiler/glsl/program.h"
#include "program/program.h"
#include "main/shaderapi.h"
#include "main/uniforms.h"
@@ -259,5 +260,6 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
if (brw->precompile && !brw_shader_precompile(ctx, shProg))
return false;
+ build_program_resource_list(shProg);
return true;
}
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
index 1b63d568d85..3f30f5b92d1 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
@@ -773,6 +773,8 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
prog_data->output_topology =
get_hw_prim_for_gl_prim(shader->info.gs.output_primitive);
+ prog_data->vertices_in = shader->info.gs.vertices_in;
+
/* The GLSL linker will have already matched up GS inputs and the outputs
* of prior stages. The driver does extend VS outputs in some cases, but
* only for legacy OpenGL or Gen4-5 hardware, neither of which offer
diff --git a/src/mesa/drivers/dri/i965/brw_wm_iz.cpp b/src/mesa/drivers/dri/i965/brw_wm_iz.cpp
index 83e1855025d..bfd14f2982d 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_iz.cpp
+++ b/src/mesa/drivers/dri/i965/brw_wm_iz.cpp
@@ -120,15 +120,14 @@ static const struct {
* \param line_aa AA_NEVER, AA_ALWAYS or AA_SOMETIMES
* \param lookup bitmask of IZ_* flags
*/
-void fs_visitor::setup_payload_gen4()
+void fs_visitor::setup_fs_payload_gen4()
{
assert(stage == MESA_SHADER_FRAGMENT);
+ brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
GLuint reg = 2;
bool kill_stats_promoted_workaround = false;
int lookup = key->iz_lookup;
- bool uses_depth =
- (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
assert(lookup < IZ_BIT_MAX);
@@ -143,7 +142,9 @@ void fs_visitor::setup_payload_gen4()
kill_stats_promoted_workaround = true;
}
- if (wm_iz_table[lookup].sd_present || uses_depth ||
+ prog_data->uses_src_depth =
+ (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
+ if (wm_iz_table[lookup].sd_present || prog_data->uses_src_depth ||
kill_stats_promoted_workaround) {
payload.source_depth_reg = reg;
reg += 2;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index ec54ef2acd9..6bf0a55e418 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -175,8 +175,7 @@ brw_upload_wm_unit(struct brw_context *brw)
}
/* BRW_NEW_FRAGMENT_PROGRAM */
- wm->wm5.program_uses_depth = (fp->Base.InputsRead &
- (1 << VARYING_SLOT_POS)) != 0;
+ wm->wm5.program_uses_depth = prog_data->uses_src_depth;
wm->wm5.program_computes_depth = (fp->Base.OutputsWritten &
BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0;
/* _NEW_BUFFERS
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 7def5f5ad3c..128c77ecf0c 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -37,9 +37,6 @@ static void
upload_wm_state(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
- /* BRW_NEW_FRAGMENT_PROGRAM */
- const struct brw_fragment_program *fp =
- brw_fragment_program_const(brw->fragment_program);
/* BRW_NEW_FS_PROG_DATA */
const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
bool writes_depth = prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF;
@@ -61,8 +58,11 @@ upload_wm_state(struct brw_context *brw)
if (ctx->Polygon.StippleFlag)
dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
- if (fp->program.Base.InputsRead & VARYING_BIT_POS)
- dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
+ if (prog_data->uses_src_depth)
+ dw1 |= GEN7_WM_USES_SOURCE_DEPTH;
+
+ if (prog_data->uses_src_w)
+ dw1 |= GEN7_WM_USES_SOURCE_W;
dw1 |= prog_data->computed_depth_mode << GEN7_WM_COMPUTED_DEPTH_MODE_SHIFT;
dw1 |= prog_data->barycentric_interp_modes <<
@@ -100,7 +100,7 @@ upload_wm_state(struct brw_context *brw)
dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
}
- if (fp->program.Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN) {
+ if (prog_data->uses_sample_mask) {
dw1 |= GEN7_WM_USES_INPUT_COVERAGE_MASK;
}
@@ -138,7 +138,6 @@ const struct brw_tracked_state gen7_wm_state = {
_NEW_MULTISAMPLE |
_NEW_POLYGON,
.brw = BRW_NEW_BATCH |
- BRW_NEW_FRAGMENT_PROGRAM |
BRW_NEW_FS_PROG_DATA,
},
.emit = upload_wm_state,
diff --git a/src/mesa/drivers/dri/i965/gen8_gs_state.c b/src/mesa/drivers/dri/i965/gen8_gs_state.c
index 6738e85eaba..c3cdb2f4350 100644
--- a/src/mesa/drivers/dri/i965/gen8_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_gs_state.c
@@ -48,7 +48,7 @@ gen8_upload_gs_state(struct brw_context *brw)
OUT_BATCH(_3DSTATE_GS << 16 | (10 - 2));
OUT_BATCH(stage_state->prog_offset);
OUT_BATCH(0);
- OUT_BATCH(brw->geometry_program->VerticesIn |
+ OUT_BATCH(brw->gs.prog_data->vertices_in |
((ALIGN(stage_state->sampler_count, 4)/4) <<
GEN6_GS_SAMPLER_COUNT_SHIFT) |
((prog_data->base.binding_table.size_bytes / 4) <<
diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c
index 74cdcef015d..b9a06e7b2c7 100644
--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
@@ -46,14 +46,17 @@ gen8_upload_ps_extra(struct brw_context *brw,
if (prog_data->num_varying_inputs != 0)
dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
- if (fp->Base.InputsRead & VARYING_BIT_POS)
- dw1 |= GEN8_PSX_USES_SOURCE_DEPTH | GEN8_PSX_USES_SOURCE_W;
+ if (prog_data->uses_src_depth)
+ dw1 |= GEN8_PSX_USES_SOURCE_DEPTH;
+
+ if (prog_data->uses_src_w)
+ dw1 |= GEN8_PSX_USES_SOURCE_W;
if (multisampled_fbo &&
_mesa_get_min_invocations_per_fragment(ctx, fp, false) > 1)
dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
- if (fp->Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN) {
+ if (prog_data->uses_sample_mask) {
if (brw->gen >= 9)
dw1 |= BRW_PSICMS_INNER << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT;
else
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
index 889f7cbb5c1..a39693b68f7 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -346,7 +346,8 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.ARB_transform_feedback3 = true;
ctx->Extensions.ARB_transform_feedback_instanced = true;
- if (ctx->Const.MaxComputeWorkGroupSize[0] >= 1024)
+ if ((brw->gen >= 8 || brw->intelScreen->cmd_parser_version >= 5) &&
+ ctx->Const.MaxComputeWorkGroupSize[0] >= 1024)
ctx->Extensions.ARB_compute_shader = true;
if (brw->intelScreen->cmd_parser_version >= 2)
diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp
index 71c5fc4a485..495048d4bfc 100644
--- a/src/mesa/program/ir_to_mesa.cpp
+++ b/src/mesa/program/ir_to_mesa.cpp
@@ -31,6 +31,7 @@
#include <stdio.h>
#include "main/compiler.h"
+#include "main/macros.h"
#include "main/mtypes.h"
#include "main/shaderapi.h"
#include "main/shaderobj.h"
@@ -3009,6 +3010,7 @@ _mesa_ir_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
_mesa_reference_program(ctx, &linked_prog, NULL);
}
+ build_program_resource_list(prog);
return prog->LinkStatus;
}
@@ -3037,8 +3039,6 @@ _mesa_glsl_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
if (prog->LinkStatus) {
if (!ctx->Driver.LinkShader(ctx, prog)) {
prog->LinkStatus = GL_FALSE;
- } else {
- build_program_resource_list(prog);
}
}
diff --git a/src/mesa/state_tracker/st_atom_shader.c b/src/mesa/state_tracker/st_atom_shader.c
index 23b7abfc1c5..c8650a5899a 100644
--- a/src/mesa/state_tracker/st_atom_shader.c
+++ b/src/mesa/state_tracker/st_atom_shader.c
@@ -172,7 +172,8 @@ update_gp( struct st_context *st )
stgp = st_geometry_program(st->ctx->GeometryProgram._Current);
assert(stgp->Base.Base.Target == GL_GEOMETRY_PROGRAM_NV);
- st->gp_variant = st_get_basic_variant(st, &stgp->tgsi, &stgp->variants);
+ st->gp_variant = st_get_basic_variant(st, PIPE_SHADER_GEOMETRY,
+ &stgp->tgsi, &stgp->variants);
st_reference_geomprog(st, &st->gp, stgp);
@@ -204,7 +205,8 @@ update_tcp( struct st_context *st )
sttcp = st_tessctrl_program(st->ctx->TessCtrlProgram._Current);
assert(sttcp->Base.Base.Target == GL_TESS_CONTROL_PROGRAM_NV);
- st->tcp_variant = st_get_basic_variant(st, &sttcp->tgsi, &sttcp->variants);
+ st->tcp_variant = st_get_basic_variant(st, PIPE_SHADER_TESS_CTRL,
+ &sttcp->tgsi, &sttcp->variants);
st_reference_tesscprog(st, &st->tcp, sttcp);
@@ -236,7 +238,8 @@ update_tep( struct st_context *st )
sttep = st_tesseval_program(st->ctx->TessEvalProgram._Current);
assert(sttep->Base.Base.Target == GL_TESS_EVALUATION_PROGRAM_NV);
- st->tep_variant = st_get_basic_variant(st, &sttep->tgsi, &sttep->variants);
+ st->tep_variant = st_get_basic_variant(st, PIPE_SHADER_TESS_EVAL,
+ &sttep->tgsi, &sttep->variants);
st_reference_tesseprog(st, &st->tep, sttep);
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index ce93aec4e71..2ad91ecf4df 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -34,6 +34,7 @@
#include "compiler/glsl/glsl_parser_extras.h"
#include "compiler/glsl/ir_optimization.h"
+#include "compiler/glsl/program.h"
#include "main/errors.h"
#include "main/shaderobj.h"
@@ -6148,6 +6149,10 @@ get_mesa_program(struct gl_context *ctx,
prog->OutputsWritten, 0ULL, prog->PatchOutputsWritten);
count_resources(v, prog);
+ /* The GLSL IR won't be needed anymore. */
+ ralloc_free(shader->ir);
+ shader->ir = NULL;
+
/* This must be done before the uniform storage is associated. */
if (shader->Type == GL_FRAGMENT_SHADER &&
(prog->InputsRead & VARYING_BIT_POS ||
@@ -6380,6 +6385,8 @@ st_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
validate_ir_tree(ir);
}
+ build_program_resource_list(prog);
+
for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
struct gl_program *linked_prog;
diff --git a/src/mesa/state_tracker/st_program.c b/src/mesa/state_tracker/st_program.c
index 624586e6d67..5bd626f8610 100644
--- a/src/mesa/state_tracker/st_program.c
+++ b/src/mesa/state_tracker/st_program.c
@@ -1271,6 +1271,7 @@ st_translate_geometry_program(struct st_context *st,
*/
struct st_basic_variant *
st_get_basic_variant(struct st_context *st,
+ unsigned pipe_shader,
struct pipe_shader_state *tgsi,
struct st_basic_variant **variants)
{
@@ -1293,7 +1294,22 @@ st_get_basic_variant(struct st_context *st,
v = CALLOC_STRUCT(st_basic_variant);
if (v) {
/* fill in new variant */
- v->driver_shader = pipe->create_gs_state(pipe, tgsi);
+ switch (pipe_shader) {
+ case PIPE_SHADER_TESS_CTRL:
+ v->driver_shader = pipe->create_tcs_state(pipe, tgsi);
+ break;
+ case PIPE_SHADER_TESS_EVAL:
+ v->driver_shader = pipe->create_tes_state(pipe, tgsi);
+ break;
+ case PIPE_SHADER_GEOMETRY:
+ v->driver_shader = pipe->create_gs_state(pipe, tgsi);
+ break;
+ default:
+ assert(!"unhandled shader type");
+ free(v);
+ return NULL;
+ }
+
v->key = key;
/* insert into list */
@@ -1587,19 +1603,19 @@ st_precompile_shader_variant(struct st_context *st,
case GL_TESS_CONTROL_PROGRAM_NV: {
struct st_tessctrl_program *p = (struct st_tessctrl_program *)prog;
- st_get_basic_variant(st, &p->tgsi, &p->variants);
+ st_get_basic_variant(st, PIPE_SHADER_TESS_CTRL, &p->tgsi, &p->variants);
break;
}
case GL_TESS_EVALUATION_PROGRAM_NV: {
struct st_tesseval_program *p = (struct st_tesseval_program *)prog;
- st_get_basic_variant(st, &p->tgsi, &p->variants);
+ st_get_basic_variant(st, PIPE_SHADER_TESS_EVAL, &p->tgsi, &p->variants);
break;
}
case GL_GEOMETRY_PROGRAM_NV: {
struct st_geometry_program *p = (struct st_geometry_program *)prog;
- st_get_basic_variant(st, &p->tgsi, &p->variants);
+ st_get_basic_variant(st, PIPE_SHADER_GEOMETRY, &p->tgsi, &p->variants);
break;
}
diff --git a/src/mesa/state_tracker/st_program.h b/src/mesa/state_tracker/st_program.h
index 7717d02cd3f..74f3def6095 100644
--- a/src/mesa/state_tracker/st_program.h
+++ b/src/mesa/state_tracker/st_program.h
@@ -352,6 +352,7 @@ st_get_fp_variant(struct st_context *st,
extern struct st_basic_variant *
st_get_basic_variant(struct st_context *st,
+ unsigned pipe_shader,
struct pipe_shader_state *tgsi,
struct st_basic_variant **variants);
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-18 20:01:10 +0000