diff options
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 41 |
1 files changed, 20 insertions, 21 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index a977ee42731..10aa5fde328 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp @@ -3815,31 +3815,30 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr unsigned read_size = instr->const_index[1] - (instr->num_components - 1) * type_sz(dest.type); - fs_reg indirect_chv_high_32bit; - bool is_chv_bxt_64bit = - (devinfo->is_cherryview || devinfo->is_broxton) && - type_sz(dest.type) == 8; - if (is_chv_bxt_64bit) { - indirect_chv_high_32bit = vgrf(glsl_type::uint_type); - /* Calculate indirect address to read high 32 bits */ - bld.ADD(indirect_chv_high_32bit, indirect, brw_imm_ud(4)); - } + bool supports_64bit_indirects = + !devinfo->is_cherryview && !devinfo->is_broxton; - for (unsigned j = 0; j < instr->num_components; j++) { - if (!is_chv_bxt_64bit) { + if (type_sz(dest.type) != 8 || supports_64bit_indirects) { + for (unsigned j = 0; j < instr->num_components; j++) { bld.emit(SHADER_OPCODE_MOV_INDIRECT, offset(dest, bld, j), offset(src, bld, j), indirect, brw_imm_ud(read_size)); - } else { - bld.emit(SHADER_OPCODE_MOV_INDIRECT, - subscript(offset(dest, bld, j), BRW_REGISTER_TYPE_UD, 0), - offset(src, bld, j), - indirect, brw_imm_ud(read_size)); - - bld.emit(SHADER_OPCODE_MOV_INDIRECT, - subscript(offset(dest, bld, j), BRW_REGISTER_TYPE_UD, 1), - offset(src, bld, j), - indirect_chv_high_32bit, brw_imm_ud(read_size)); + } + } else { + const unsigned num_mov_indirects = + type_sz(dest.type) / type_sz(BRW_REGISTER_TYPE_UD); + /* We read a little bit less per MOV INDIRECT, as they are now + * 32-bits ones instead of 64-bit. Fix read_size then. + */ + const unsigned read_size_32bit = read_size - + (num_mov_indirects - 1) * type_sz(BRW_REGISTER_TYPE_UD); + for (unsigned j = 0; j < instr->num_components; j++) { + for (unsigned i = 0; i < num_mov_indirects; i++) { + bld.emit(SHADER_OPCODE_MOV_INDIRECT, + subscript(offset(dest, bld, j), BRW_REGISTER_TYPE_UD, i), + subscript(offset(src, bld, j), BRW_REGISTER_TYPE_UD, i), + indirect, brw_imm_ud(read_size_32bit)); + } } } } |