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Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/genX_state_upload.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index 533ef8b7033..04a492539a9 100644 --- a/src/mesa/drivers/dri/i965/genX_state_upload.c +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c @@ -4169,6 +4169,18 @@ genX(upload_cs_state)(struct brw_context *brw) uint32_t *bind = brw_state_batch(brw, prog_data->binding_table.size_bytes, 32, &stage_state->bind_bo_offset); + /* The MEDIA_VFE_STATE documentation for Gen8+ says: + * + * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless + * the only bits that are changed are scoreboard related: Scoreboard + * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For + * these scoreboard related states, a MEDIA_STATE_FLUSH is sufficient." + * + * Earlier generations say "MI_FLUSH" instead of "stalling PIPE_CONTROL", + * but MI_FLUSH isn't really a thing, so we assume they meant PIPE_CONTROL. + */ + brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL); + brw_batch_emit(brw, GENX(MEDIA_VFE_STATE), vfe) { if (prog_data->total_scratch) { uint32_t bo_offset; |