3 files changed, 59 insertions, 20 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 8e01877a630..b77b44e08b6 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -536,7 +536,8 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
      
       brw_render_cache_set_add_bo(brw, irb->mt->bo);
       intel_miptree_finish_render(brw, irb->mt, irb->mt_level,
-                                  irb->mt_layer, irb->layer_count);
+                                  irb->mt_layer, irb->layer_count,
+                                  ctx->Color.sRGBEnabled);
    }
 }
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index ae3a226ba6a..37afaa58953 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2505,38 +2505,71 @@ intel_miptree_prepare_fb_fetch(struct brw_context *brw,
                                         start_layer, num_layers, NULL);
 }
 
-void
-intel_miptree_prepare_render(struct brw_context *brw,
-                             struct intel_mipmap_tree *mt, uint32_t level,
-                             uint32_t start_layer, uint32_t layer_count,
-                             bool srgb_enabled)
+enum isl_aux_usage
+intel_miptree_render_aux_usage(struct brw_context *brw,
+                               struct intel_mipmap_tree *mt,
+                               bool srgb_enabled)
 {
-   /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
-    * the single-sampled color renderbuffers because the CCS buffer isn't
-    * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
-    * enabled because otherwise the surface state will be programmed with
-    * the linear equivalent format anyway.
-    */
-   if (brw->gen == 9 && srgb_enabled && mt->surf.samples == 1 &&
-       _mesa_get_srgb_format_linear(mt->format) != mt->format) {
+   switch (mt->aux_usage) {
+   case ISL_AUX_USAGE_MCS:
+      assert(mt->mcs_buf);
+      return ISL_AUX_USAGE_MCS;
+
+   case ISL_AUX_USAGE_CCS_D:
+      /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
+       * the single-sampled color renderbuffers because the CCS buffer isn't
+       * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
+       * enabled because otherwise the surface state will be programmed with
+       * the linear equivalent format anyway.
+       */
+      if (srgb_enabled &&
+          _mesa_get_srgb_format_linear(mt->format) != mt->format) {
+         return ISL_AUX_USAGE_NONE;
+      } else if (!mt->mcs_buf) {
+         return ISL_AUX_USAGE_NONE;
+      } else {
+         return ISL_AUX_USAGE_CCS_D;
+      }
 
+   case ISL_AUX_USAGE_CCS_E: {
       /* Lossless compression is not supported for SRGB formats, it
        * should be impossible to get here with such surfaces.
        */
-      assert(mt->aux_usage != ISL_AUX_USAGE_CCS_E);
-      intel_miptree_prepare_access(brw, mt, level, 1, start_layer, layer_count,
-                                   false, false);
+      assert(!srgb_enabled ||
+             _mesa_get_srgb_format_linear(mt->format) == mt->format);
+
+      return ISL_AUX_USAGE_CCS_E;
+   }
+
+   default:
+      return ISL_AUX_USAGE_NONE;
    }
 }
 
 void
+intel_miptree_prepare_render(struct brw_context *brw,
+                             struct intel_mipmap_tree *mt, uint32_t level,
+                             uint32_t start_layer, uint32_t layer_count,
+                             bool srgb_enabled)
+{
+   enum isl_aux_usage aux_usage =
+      intel_miptree_render_aux_usage(brw, mt, srgb_enabled);
+   intel_miptree_prepare_access(brw, mt, level, 1, start_layer, layer_count,
+                                aux_usage, aux_usage != ISL_AUX_USAGE_NONE);
+}
+
+void
 intel_miptree_finish_render(struct brw_context *brw,
                             struct intel_mipmap_tree *mt, uint32_t level,
-                            uint32_t start_layer, uint32_t layer_count)
+                            uint32_t start_layer, uint32_t layer_count,
+                            bool srgb_enabled)
 {
    assert(_mesa_is_format_color_format(mt->format));
+
+   enum isl_aux_usage aux_usage =
+      intel_miptree_render_aux_usage(brw, mt, srgb_enabled);
    intel_miptree_finish_write(brw, mt, level, start_layer, layer_count,
-                              mt->mcs_buf != NULL);
+                              aux_usage != ISL_AUX_USAGE_NONE);
 }
 
 void
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index fbb6b9cd83f..583a75103ef 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -626,6 +626,10 @@ void
 intel_miptree_prepare_fb_fetch(struct brw_context *brw,
                                struct intel_mipmap_tree *mt, uint32_t level,
                                uint32_t start_layer, uint32_t num_layers);
+enum isl_aux_usage
+intel_miptree_render_aux_usage(struct brw_context *brw,
+                               struct intel_mipmap_tree *mt,
+                               bool srgb_enabled);
 void
 intel_miptree_prepare_render(struct brw_context *brw,
                              struct intel_mipmap_tree *mt, uint32_t level,
@@ -634,7 +638,8 @@ intel_miptree_prepare_render(struct brw_context *brw,
 void
 intel_miptree_finish_render(struct brw_context *brw,
                             struct intel_mipmap_tree *mt, uint32_t level,
-                            uint32_t start_layer, uint32_t layer_count);
+                            uint32_t start_layer, uint32_t layer_count,
+                            bool srgb_enabled);
 void
 intel_miptree_prepare_depth(struct brw_context *brw,
                             struct intel_mipmap_tree *mt, uint32_t level,