diff options
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_screen.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 7f6b69713c1..5041acd9a71 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -96,6 +96,7 @@ DRI_CONF_BEGIN DRI_CONF_SECTION_MISCELLANEOUS DRI_CONF_GLSL_ZERO_INIT("false") DRI_CONF_ALLOW_RGB10_CONFIGS("false") + DRI_CONF_ALLOW_RGB565_CONFIGS("true") DRI_CONF_SECTION_END DRI_CONF_END }; @@ -2198,6 +2199,9 @@ intel_screen_make_configs(__DRIscreen *dri_screen) /* Shall we expose 10 bpc formats? */ bool allow_rgb10_configs = driQueryOptionb(&screen->optionCache, "allow_rgb10_configs"); + /* Shall we expose 565 formats? */ + bool allow_rgb565_configs = driQueryOptionb(&screen->optionCache, + "allow_rgb565_configs"); /* Generate singlesample configs, each without accumulation buffer * and with EGL_MUTABLE_RENDER_BUFFER_BIT_KHR. @@ -2211,6 +2215,9 @@ intel_screen_make_configs(__DRIscreen *dri_screen) formats[i] == MESA_FORMAT_B10G10R10X2_UNORM)) continue; + if (!allow_rgb565_configs && formats[i] == MESA_FORMAT_B5G6R5_UNORM) + continue; + /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil * buffer that has a different number of bits per pixel than the color * buffer, gen >= 6 supports this. @@ -2253,6 +2260,9 @@ intel_screen_make_configs(__DRIscreen *dri_screen) formats[i] == MESA_FORMAT_B10G10R10X2_UNORM)) continue; + if (!allow_rgb565_configs && formats[i] == MESA_FORMAT_B5G6R5_UNORM) + continue; + if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) { depth_bits[0] = 16; stencil_bits[0] = 0; @@ -2291,6 +2301,9 @@ intel_screen_make_configs(__DRIscreen *dri_screen) formats[i] == MESA_FORMAT_B10G10R10X2_UNORM)) continue; + if (!allow_rgb565_configs && formats[i] == MESA_FORMAT_B5G6R5_UNORM) + continue; + __DRIconfig **new_configs; const int num_depth_stencil_bits = 2; int num_msaa_modes = 0; |