diff options
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 7 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 9 |
2 files changed, 16 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 2a8dbf8cb9a..4abb790612d 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1617,6 +1617,13 @@ enum brw_pixel_shader_coverage_mask_mode { # define GEN8_HIZ_PMA_MASK_BITS \ REG_MASK(GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE) +#define GEN7_GT_MODE 0x7008 +# define GEN9_SUBSLICE_HASHING_8x8 (0 << 8) +# define GEN9_SUBSLICE_HASHING_16x4 (1 << 8) +# define GEN9_SUBSLICE_HASHING_8x4 (2 << 8) +# define GEN9_SUBSLICE_HASHING_16x16 (3 << 8) +# define GEN9_SUBSLICE_HASHING_MASK_BITS REG_MASK(3 << 8) + /* Predicate registers */ #define MI_PREDICATE_SRC0 0x2400 #define MI_PREDICATE_SRC1 0x2408 diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index acaa97ee7d4..f38c1946df6 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -72,6 +72,15 @@ brw_upload_initial_gpu_state(struct brw_context *brw) GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE | GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC); ADVANCE_BATCH(); + + if (brw->is_broxton) { + BEGIN_BATCH(3); + OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); + OUT_BATCH(GEN7_GT_MODE); + OUT_BATCH(GEN9_SUBSLICE_HASHING_MASK_BITS | + GEN9_SUBSLICE_HASHING_16x16); + ADVANCE_BATCH(); + } } if (brw->gen >= 8) { |