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-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_generator.cpp4
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_generator.cpp4
-rw-r--r--src/mesa/drivers/dri/i965/gen8_fs_generator.cpp4
-rw-r--r--src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp4
4 files changed, 8 insertions, 8 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 8e4a31d951f..8a7fa92738d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -576,11 +576,11 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
* exclusively use the offset - we have to use both.
*/
assert(brw->gen >= 8 || brw->is_haswell);
+ const int sampler_state_size = 16; /* 16 bytes */
brw_ADD(p,
get_element_ud(header_reg, 3),
get_element_ud(brw_vec8_grf(0, 0), 3),
- brw_imm_ud(16 * (inst->sampler / 16) *
- sizeof(gen7_sampler_state)));
+ brw_imm_ud(16 * (inst->sampler / 16) * sampler_state_size));
}
brw_pop_insn_state(p);
}
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 5266f81ed7c..c328f349bc9 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -347,12 +347,12 @@ vec4_generator::generate_tex(vec4_instruction *inst,
* offset, and each sampler state is only 16-bytes, so we can't
* exclusively use the offset - we have to use both.
*/
+ const int sampler_state_size = 16; /* 16 bytes */
assert(brw->gen >= 8 || brw->is_haswell);
brw_ADD(p,
get_element_ud(header, 3),
get_element_ud(brw_vec8_grf(0, 0), 3),
- brw_imm_ud(16 * (inst->sampler / 16) *
- sizeof(gen7_sampler_state)));
+ brw_imm_ud(16 * (inst->sampler / 16) * sampler_state_size));
}
brw_pop_insn_state(p);
}
diff --git a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
index 4f0cf70bf6a..4e53d155bac 100644
--- a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
@@ -267,11 +267,11 @@ gen8_fs_generator::generate_tex(fs_inst *ir,
* offset, and each sampler state is only 16-bytes, so we can't
* exclusively use the offset - we have to use both.
*/
+ const int sampler_state_size = 16; /* 16 bytes */
gen8_instruction *add =
ADD(get_element_ud(src, 3),
get_element_ud(brw_vec8_grf(0, 0), 3),
- brw_imm_ud(16 * (ir->sampler / 16) *
- sizeof(gen7_sampler_state)));
+ brw_imm_ud(16 * (ir->sampler / 16) * sampler_state_size));
gen8_set_mask_control(add, BRW_MASK_DISABLE);
}
diff --git a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
index 4f9b2a3774e..ee8e85ef992 100644
--- a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
@@ -122,11 +122,11 @@ gen8_vec4_generator::generate_tex(vec4_instruction *ir, struct brw_reg dst)
* offset, and each sampler state is only 16-bytes, so we can't
* exclusively use the offset - we have to use both.
*/
+ const int sampler_state_size = 16; /* 16 bytes */
gen8_instruction *add =
ADD(get_element_ud(brw_message_reg(ir->base_mrf), 3),
get_element_ud(brw_vec8_grf(0, 0), 3),
- brw_imm_ud(16 * (ir->sampler / 16) *
- sizeof(gen7_sampler_state)));
+ brw_imm_ud(16 * (ir->sampler / 16) * sampler_state_size));
gen8_set_mask_control(add, BRW_MASK_DISABLE);
}